Multiphase-clock processing circuit and clock multiplying...

Details Multiphase-clock processing circuit and clock multiplying... Multiphase-clock processing circuit and clock multiplying...

2005-11-22

2005-11-22

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S298000, C327S112000, C326S085000, C326S087000

Reexamination Certificate

active

06967512

ABSTRACT:
In a circuit block BL1, a PMOS transistor P1and a PMOS transistor P1′ are connected in series between a high-level potential HL and an output terminal U1; an NMOS transistor N1and an NMOS transistor N1′ are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1is inputted to the gate of the PMOS transistor P1′ through an inverter IV1; a clock signal Ck2is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2is inputted to the gate of the NMOS transister N1′ through an inverter IV2.

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Communication from Chinese Patent Office re: counterpart application.

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