Multimode interpolation filter as for a TV receiver

Details Multimode interpolation filter as for a TV receiver Multimode interpolation filter as for a TV receiver

1998-05-13

2002-12-31

Miller, John W. (Department: 2614)

Television

Format conversion

C348S443000, C348S445000, C348S448000, C348S440100, C348S450000, C348S453000

Reexamination Certificate

active

06501507

ABSTRACT:

This invention relates to an interpolator for scan converting decompressed video signal occurring in a plurality of alternative formats.
BACKGROUND OF THE INVENTION
With the advent of compressed video signal transmissions, it is anticipated that receiver apparatus, to be competitive, will be expected to display images in a standardized format regardless of the format of the transmitted video data. For example, video signal compressed according to the MPEG 2 format (Moving Pictures Expert Group of the International Standardization Organization) may represent images in 4:2:2 format; 4:2:0 format and various other formats. Regardless of the transmitted format, the receiver should display all images in, for example, the 4:2:2 format.
There are many known systems for performing scan conversion from one format to another. Nominally such systems are optimized to convert one specific signal format to a second specific signal format. However, in the environment of a television receiver it is not practical to include a plurality of optimized scan converters, one for each anticipated transmitted signal format. Rather a compromise approach must be taken to scan conversion, where a plurality of signal formats may be converted in a single converter apparatus with acceptable rather than optimized performance.
Consider the MPEG 2 standard which supports different compression processes as well as different resolution formats. The different compression processes include intra-frame and intra-field processing.
Raw data from an MPEG decoding process is frames of video signal. A full resolution frame (4:2:0) consists of 480 lines of luminance signal and 240 lines of chrominance signal. A half resolution (4:2:0) includes 240 lines of luminance signal and 120 lines of chrominance signal. In the full resolution mode the decoded lines may be numbered
Y
1
, Y
2
, Y
3
, Y
4
, Y
5
, Y
6
. . . Y
480
C
1
, C
2
, C
3
, C
4
, . . . C
240
and in the half resolution mode the decoded lines may be numbered
Y
1
, Y
2
, Y
3
, Y
4
, Y
5
, Y
6
. . . Y
240
C
1
, C
2
, C
3
, C
4
, . . . C
120
.
The output of the MPEG decoder is always twice as many luminance lines as chrominance lines. However the desired output 4:2:2 display format may be represented
OY
1
, OY
2
, OY
3
, OY
4
, . . . OY
480
OC
1
, OC
2
, OC
3
, OC
4
, . . . OC
480
.
Regardless of the original resolution, the number of chrominance lines is up-converted. In the half resolution mode, the number of luminance lines is also up-converted. The mode of up-conversion may be variable depending upon the preprocessing implemented prior to the compression process used in developing the compressed signal. Certain modes of up-conversion are more conducive to up-converting intra-fame preprocessed signal and other modes are more conducive to up-converting inter-field preprocessed signal. The present invention is an interpolator for performing just such multi-mode vertical up-conversion of video signal.
SUMMARY OF THE INVENTION
The present interpolator includes a delay element for delaying one horizontal line of video signal and selectively re-displaying that line. A multiplexer is arranged to selectively provide either decoded luminance signal or decoded chrominance signal to the delay element. Output signal from the delay element and output signal from the multiplexer are coupled to a proportioning circuit which sums the two signals in complementary proportions (e.g. K and 1-K). A second multiplexer, which provides up-converted output luminance signal, is arranged to selectively pass the decoded luminance signal or signal from the proportioning circuit. A third multiplexer, which provides up-converted output chrominance signal, is arranged to selectively pass the decoded chrominance signal or signal from the proportioning circuit.


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