Multimaster CPU system with early memory addressing

Details Multimaster CPU system with early memory addressing Multimaster CPU system with early memory addressing

1983-02-28

1986-10-28

Thomas, James D.

Boots, shoes, and leggings

G06F 1200

Patent

active

046202773

ABSTRACT:
A circuit and technique of operation thereof are disclosed for a multimaster CPU system wherein a memory may be accessed during program operation in an average time less than that of the memory access time specification. This technique has particular usefulness in programs contained in relatively slow read-only-memory wherein a significant portion of the addresses related to memory are sequential. In optimum utilization, each master CPU has a dedicated PROM card which can only be enabled by the specified CPU. This configuration prevents additional master CPU's from interfering with the time saving benefits of early memory addressing.

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L. J. Scanlon, "The 6800: Principles and Programming", Chapter 6, 1981, Sams Publishing Co.
"Caps-6 Central Processing Unit", Rockwell International Corporation.

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