Multilevel metallization process for use in fabricating microele

Details Multilevel metallization process for use in fabricating microele Multilevel metallization process for use in fabricating microele

1995-01-27

1996-09-10

Carroll, D. J.

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

257635, 257637, 257644, 257650, 437189, 437195, 437235, 437982, H01L 2358

Patent

active

055548849

ABSTRACT:
A multilevel metallization is deposited on a microelectronic device base structure (40). The process includes depositing a glassy dielectric layer (48) of a thickness that is from about two to about three times as thick as the topography thickness (D) of the base structure (40). The glassy dielectric layer (48) is heated to a temperature above its glass transition temperature to flow the glassy dielectric layer (48). The glassy dielectric layer (48) is thinned to a preselected thickness, and a first patterned metallization layer (54) is deposited. The process further includes depositing an interlevel dielectric layer (58), dry etching the interlevel dielectric layer (58) to thin the interlevel dielectric layer (58) and, optionally, depositing additional interlevel dielectric layer (58') material to achieve a preselected thickness. A second patterned metallization layer (64) is deposited over the interlevel dielectric layer ( 58/58').

REFERENCES:
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patent: 4686000 (1987-08-01), Heath
patent: 4900690 (1990-02-01), Tamura
patent: 5114530 (1992-05-01), Rao et al.
patent: 5143820 (1992-09-01), Kotecha et al.
Stanley Wolf, "Silicon Processing for the VLSI Era; vol. 2: Process Integration", Lattice Press, (1990), pp. 212-214 and p. 288.

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