Multilevel logic circuit with floating node voltage clamp

Details Multilevel logic circuit with floating node voltage clamp Multilevel logic circuit with floating node voltage clamp

1987-12-04

1989-04-18

Miller, Stanley D.

Cutlery

307455, 307544, 307558, 307443, 307358, H03K 19086, H03K 19092, H03K 19003, H03K 1716

Patent

active

048230286

ABSTRACT:
A multilevel logic circuit includes a pair of resistors coupling collectors of an emitter-coupled pair of transistors to a voltage source, and includes a switch selectively connecting the emitters of the transistors to a current source. When the switch is closed, an input signal applied across the bases of the transistors controls an output signal produced between their collectors. When the switch is open, both transistors are off and the output signal is not affected by the input signal. A clamping circuit connected to a circuit node at the emitters of the transistors maintains a constant voltage at the node sufficient to prevent leakage current from charging or discharging inherent circuit capacitance at the node when the switch is open. Since the voltage of the node remains substantially unchanged after the switch opens, the current from the current source need not substantially charge or discharge this inherent capacitance when the switch subsequently closes in order to permit a transistor of the emitter-coupled pair to turn on.

REFERENCES:
patent: 4532440 (1985-07-01), Barre
patent: 4560888 (1985-12-01), Oida
patent: 4647799 (1987-03-01), Hsu et al.
patent: 4682058 (1987-07-01), Gal
patent: 4686394 (1987-08-01), Lam
patent: 4691120 (1987-09-01), Kondo
patent: 4748346 (1988-05-01), Emori

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