Multilevel interrupt handling scheme

Details Multilevel interrupt handling scheme Multilevel interrupt handling scheme

1985-04-01

1988-03-29

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 900

Patent

active

047348828

ABSTRACT:
An interrupt request handling mechanism employs a portion of the address portion of the data processing system's communication bus. All interrupt requests to a processor are handled by an associated interrupt controller that is coupled between the prescribed address lines and the processor. As interrupt requests are received they are temporarily stored in memory. The storage locations of the memory are successively scanned, beginning with the memory address having the highest priority level and proceeding through successively lesser orders of priority locations until an interrupt request has been found. That located "highest" priority level interrupt request that is stored in memory is placed in a buffer register the contents of which are compared, on a continual basis, with the level of the task being executed by the processor. Upon the level of the task under execution by the processor falling below that associated with the contents of the buffer register, the interrupt controller couples the contents of the buffer register to the processor as an interrupt. When the processor acknowledges capture of the interrupt from the interrupt controller, the corresponding storage location in memory is erased.

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