Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1998-02-20
1999-01-19
Saadat, Mahshid D.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257759, 257522, 257506, H01L 2348, H01L 2352, H01L 2940
Patent
active
058616748
ABSTRACT:
In a multilevel interconnection structure for a semiconductor device, lower level interconnections 3 are formed on an insulator film 2 formed on a substrate 1, and a silicon oxide film 4a is formed to cover the lower level interconnections 3 and to fill up a region between adjacent lower level interconnections 3, by means of a biased ECR-CVD process so that a cavity 5 is formed in the silicon oxide film 4a between the adjacent lower level interconnections 3. The silicon oxide film 4a is selectively removed from a tolerable region covering the extent in which a hole for the metal pillar 6 is allowed to deviate from a target lower level interconnection 3, and then, another silicon oxide 4b is formed to fill up the removed portion and to cover the first silicon oxide film. The metal pillar 6 is formed to extend through the silicon oxide film 4b filling the removed portion of the silicon oxide film 4a, so as to reach the target lower level interconnection 3. On the metal pillar 6, an upper level interconnection 7 is formed. Thus, since the cavity 5 is completely surrounded by the silicon oxide film 4a, a contact between the cavity 5 and the metal pillar 6 is completely prevented by the silicon oxide film 4a.
REFERENCES:
patent: 5310700 (1994-05-01), Lein et al.
patent: 5539227 (1996-07-01), Nakano
patent: 5783864 (1998-07-01), Dawson et al.
patent: 5789807 (1997-08-01), Correale, Jr.
Clark S. V.
NEC Corporation
Saadat Mahshid D.
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