Multilevel interconnect system for high density silicon gate fie

Details Multilevel interconnect system for high density silicon gate fie Multilevel interconnect system for high density silicon gate fie

1979-09-05

1982-03-09

Larkins, William D.

357 54, 357 59, 357 63, H01L 29167, H01L 2978

Patent

active

043192602

ABSTRACT:
A metal oxide semiconductor device having at least one level of polycrystalline silicon interconnects and novel insulation layers for multilevel interconnects. In one embodiment a layer of arsenic doped glass replaces the conventional phosphorus doped glass insulation layer. In other embodiments a layer of arsenic doped glass upon an undoped layer of silicon dioxide provides the insulation layer. Slow diffusing source-drain impurities along with these insulation layers provide minimum lateral source-drain diffusion.

REFERENCES:
patent: 3571914 (1971-03-01), Lands et al.
patent: 3798081 (1974-03-01), Beyer
patent: 4013489 (1977-03-01), Oldham

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