Multilevel interconnect structure of an integrated circuit forme

Details Multilevel interconnect structure of an integrated circuit forme Multilevel interconnect structure of an integrated circuit forme

1996-06-05

1997-10-21

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437192, 437195, H01L 21441

Patent

active

056796056

ABSTRACT:
A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via is filled with a conductive material which forms a plug separate from the material used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric to underlying conductors. A second dielectric is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure is left substantially planar in readiness for subsequent interconnect levels dielectically deposited thereon.

REFERENCES:
patent: 5451543 (1995-09-01), Woo et al.
patent: 5514622 (1996-05-01), Bornstein et al.
patent: 5580825 (1996-12-01), Labunov et al.
patent: 5587339 (1996-12-01), Wyborn et al.

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