Multilevel interconnect structure and method of manufacturing th

Details Multilevel interconnect structure and method of manufacturing th Multilevel interconnect structure and method of manufacturing th

1992-10-23

1994-04-26

Arbes, Carl J.

Metal working

Method of mechanical manufacture

Electrical device making

156646, 437192, H01K 310

Patent

active

053055195

ABSTRACT:
A multilevel interconnect structure for use in a semiconductor device including a lower metal wiring which is formed by selectively etching a stack of an aluminum alloy film deposited on a silicon substrate via an underlying insulating film and a TiW film deposited on the aluminum alloy film, an interlayer insulating film deposited on the lower metal wiring, a via hole formed in the interlayer insulating film such that the aluminum alloy film of the lower metal wiring is exposed in a bottom of the via hole, a plug made of aluminum and formed in the via hole such that a lower end of the plug is directly contacted with the aluminum alloy film of the lower metal wiring, and an upper metal wiring having an aluminum alloy film formed on the interlayer insulating film such that an upper end of the plug is directly contacted with the aluminum alloy film of the upper metal wiring. Since the upper and lower metal wirings are electrically connected to each other via interfaces of aluminum-aluminum alloy, the via resistance can be decreased and the electromigration reliability can be improved.

REFERENCES:
patent: 4172009 (1979-10-01), Alcorn et al.
patent: 4824802 (1989-04-01), Brown et al.
Abstract of a Paper by J. Onoe and H. Yamamoto in Proc. Workshop, 6th Meeting date 1989 pp. 325-331, Ed. by S. Wong & F. Furukawa, Mater. Res. Soc: Pittsburgh, Pa. 1990.
IEEE Electron Device Letters vol. EDL-8 No. 2 Feb. 1987, pp. 76-78 by R. Mukai et al.
Proceedings of ECS Symposia, vol. 89-6 pp. 26-38, 1989.
Stress Induced Migration of Aluminum-Silicon Films: Influencing Factors and Countermeasures.
Reprint from Proceedings of the IEDM-Dec. 6-9, 1987, pp. 205-208.
Reliable Tungsten Encapsulated Al-Si Interconnects for Submicron Multilevel Interconnect.
VMIC Conference, Jun. 12-13, 1990, pp. 42-48.
A High Performance Four Metal Layer Interconnect System for Bipolar and BiCMOS Circuits.
VMIC Conferernce, Jun. 12-13, 1990, pp. 21-27.
An Advanced Four Level Interconnect Enhancement Module For 0.9 Micron CMOS.
VMIC Conference, Jun. 12-13, 1990, pp. 106-111.
Electromigration in a Two-Level Al-Cu Interconnection with W Studs.
IEEE Transactions on Electron Devices, vol. 37, No. 3, Mar. 1990, pp. 562-567.
Electromigration Reliability for a Tungsten-Filled Via Hole Structure.

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