Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-01-11
2003-07-15
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S768000
Reexamination Certificate
active
06593656
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the manufacturing of integrated circuits. In particular, this invention relates to using a thin copper oxide film as a seed layer for building multilevel interconnects structures in integrated circuits.
BACKGROUND OF THE INVENTION
The rapid progress in miniaturization of integrated circuits (IC) is leading to denser and finer pitched chips with ever increasing performance. In order to enhance the performance of advanced ICs, interconnect systems are gradually migrating away from aluminum thin films to copper thin films. As compared to aluminum, a traditionally used material, copper has more advantages, which are critical for improving integrated circuit performance. First, copper has a much lower sheet resistivity than aluminum. Thus, for carrying the same amount of current, a copper line can be made narrower and thinner than an aluminum one. Therefore, using a copper line allows for higher integration density. Also, narrower and thinner conductive lines decrease both inter-level and inter-line capacitance, which leads to higher speed and less bleed over for the circuit. Lastly, copper has a better electromigration resistance than aluminum. Accordingly, as metal lines are made thinner and circuitry becomes more densely packed, copper provides higher reliability when used in ICs.
Of the several methods proposed for fabricating copper interconnects, the most promising method appears to be the Damascene process. In using this method, the trenches and vias are formed in blanket dielectrics, and then a metal is deposited into the trenches and holes in one step, which is then followed by chemical mechanical planarization (CMP) to remove the unwanted surface metal. This leaves the desired metal in the trenches and holes, and a planarized surface for subsequent processsing.
However, during the aforementioned CMP process, especially for the vias, more than ninety-nine percent of the deposited copper is removed. In terms of copper alone, this is very wasteful and expensive. In addition, manufacturing consumables, such as pads and slurries are excessively consumed during the CMP process. The disposal of these manufacturing by-products is of sufficient environmental concern to warrant a more viable method. Therefore, it is highly desirable to accomplish the copper metallization without CMP. A selective copper deposition by electroless plating or chemical vaporization deposition (CVD) offers a “CMP-less” metallization technology. For example, one such method of fabricating multilayer interconnect structures using electroless selectively deposited copper is described in a previously co-pending application entitled “A SELECTIVE ELECTROLESS-PLATED MULTILAYER COPPER METALLIZATION FOR ULSI,” Micron Docket No. 99-0715, which is incorporated herein by reference. In that method, a very thin film of Pd or Cu, forms an “island structure” or a barely continuous thin film in the thickness range of 3-10 nm.
SUMMARY OF THE INVENTION
In one aspect of the invention, multilevel copper interconnects, including metal lines and via holes, are fabricated on a wafer. Initially, a thin seed layer of copper oxide is deposited over the wafer. After defining the metal line pattern by standard optical lithography, the exposed copper oxide is converted to copper using an ultra-violet photo reduction method. Afterwards, a copper film is deposited using electroless plating or chemical vaporization deposition (CVD) and a planar surface is thereby provided. In the next step, via holes are fabricated using conventional methods such as via hole lithography, and a second layer of copper oxide is deposited in a manner similar to the first. As with the first copper layer, a planar surface is provided for subsequent layers.
As a result, multilevel interconnect structures with as many metal layers as desired can be manufactured by repeating the process, and without the need for CMP. One key advantage of using copper oxide in lieu of copper as the seed layer is the potentially high manufacturing yield in ICs. If a pure copper seed layer is used, a native copper oxide may form on the surface of the wafer depending upon how long the wafer is exposed to the air. This makes reproducibility an issue unless an additional step of removing the copper oxide is performed.
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Ahn Kie Y.
Geusic Joseph E.
Micro)n Technology, Inc.
Tsai Jey
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