Multilevel controller for a cache memory interface in a multipro

Details Multilevel controller for a cache memory interface in a multipro Multilevel controller for a cache memory interface in a multipro

1983-04-05

1986-04-29

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300, G06F 1516, G06F 1200

Patent

active

045861331

ABSTRACT:
A two-level controller for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities. The two-level controller is formed of a hierarchy of two control stores wherein the receipt of a command code by the first control store from the processor causes it to address the second control store. Each control store is provided with program counter means to receive its respective address and to increment that address until it receives a new address so as to asynchronously control simultaneous operation of a memory interface to said memory modules and a cache mechanism coupled to the processor.

REFERENCES:
patent: 4038643 (1977-07-01), Kim
patent: 4075686 (1978-02-01), Calle et al.
patent: 4156278 (1979-05-01), Wilhite
patent: 4168523 (1979-09-01), Chari et al.
patent: 4179736 (1979-12-01), Wilhite
patent: 4217640 (1980-08-01), Porter et al.
patent: 4251862 (1981-02-01), Murayama
patent: 4268907 (1981-05-01), Porter et al.
patent: 4307445 (1981-12-01), Tredennick et al.
patent: 4313158 (1982-01-01), Porter et al.
patent: 4376976 (1983-03-01), Lahti et al.
patent: 4433374 (1984-02-01), Hanson et al.
patent: 4467415 (1984-08-01), Ogawa

Affiliated with

Also associated with

Rating

Multilevel controller for a cache memory interface in a multipro does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilevel controller for a cache memory interface in a multipro, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilevel controller for a cache memory interface in a multipro will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-145010