Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2000-02-25
2001-04-17
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185190, C365S185290
Reexamination Certificate
active
06219276
ABSTRACT:
BACKGROUND
A flash memory cell can be a field effect transistor (FET) that includes a select gate, a floating gate, a drain, and a source. A memory cell can be read by grounding the source, and applying a voltage to a bitline connected with the drain. By applying a voltage to the wordline connected to select gate, the cell can be switched on and off.
Programming a memory cell includes trapping excess electrons in the floating gate to increase voltage. This reduces the current conducted by the memory cell when the select voltage is applied to the select gate. The memory cell is programmed when the memory cell current is less than a reference current and the select voltage is applied. The memory cell is erased when the memory cell current is greater than the reference current and the select voltage is applied.
Memory cells with only two programmable states contain only a single bit of information, such as a “0” or a “1”.
A multi-level cell (“MLC”) can be programmed with more than one voltage level. Each voltage level is mapped to corresponding bits of information. For example, a multi-level cell is programmed with one of four voltage levels, −2.5V, 0.0V, +1.0V, +2.0V that correspond to binary “00”, “01”, “10”, and “11”, respectively. A cell that is programmable at more voltage levels can store more bits of data based on the following equation:
N=2{circumflex over ( )}B Eqn. 1
B is the number of bits of data stored
N is the number of voltage levels.
Thus, a 1 bit cell requires 2 voltage levels, a 2 bit cell requires 4 voltage levels, a 3 bit cell requires 8 voltage levels, and a 4 bit cell requires 16 voltage levels.
Two of the primary data reliability issues for memory cells, particularly NAND flash, are the “data retention” effect and “read disturb” effect. The “data retention” effect is a shift in voltage that results from the normal passage of time. This shift is toward the erase state. The “read disturb” effect is a shift in the voltage that results from reading the memory cell. For the read disturb effect to be appreciable, many reads must occur. The read disturb effect and the data retention effect shift the voltage in opposite directions.
When the voltage level shifts too far in either direction, it will be interpreted as representing the next higher or lower voltage level and thus the data will be misread. To prevent such misreads, the “data retention” effect and “read disturb” effect should be optimized to minimize the voltage shifts.
FIG. 1
shows a representation of a four level multilevel cell program voltage diagram
100
. The program voltage distribution (“distribution”) of the four levels are shown between lines
102
and
104
,
106
and
108
, lines
110
and
112
, and above line
114
, respectively. The programming distribution can be for example 100 mV to 600 mV wide. A four level multilevel memory cell can be programmed with any one of these voltage levels. Because the cell can store one of four binary values it can store 2 bits of information. The data margin (“margin”), also called a guard band, is the voltage levels between distributions that is not normally used. The margins are shown in
FIG. 1
between lines
104
and
106
; lines
108
and
110
; and lines
112
and
114
. For example, the data margin can be 800 mV to 100 mV wide.
FIG. 2
shows the affect of the phenomena called “read disturb.” Read disturb occurs after the cell has been read many times without being reprogrammed. The programming distributions are shifted to the right, which represents a positive voltage shift. Distributions
230
,
232
,
234
, and
236
represent the distributions
220
,
222
,
224
, and
226
after they have been affected by the read disturb. Eventually, the read disturb can become so severe that the stored data becomes unreliable, such as at lines
210
and
212
.
FIG. 3
shows the affect of the phenomena called “data retention.” Data retention causes the distributions
220
,
222
,
224
, and
226
to be shifted to the left as shown by distributions
320
,
322
,
324
, and
326
, which represents a negative voltage shift. Over time if the cell is not reprogrammed, the data retention shift can cause the stored data to become unreliable.
BRIEF SUMMARY OF THE PREFERRED EMBODIMENTS
Method of storing and retrieving multiple bits of information in a multi-level cell of non-volatile memory including programming a plurality of multi-level memory cells within a programming time target. The multi-level memory cells having at least first, second, third and fourth programming levels. The fourth programming level being the erase state, the first programming level being the programming level furthest from the fourth programming level. The second and third programming levels being within the first and fourth programming levels, includes erasing the plurality of multi-level memory cells. Then, programming a first group of multi-level memory cells with the first programming level with a first programming pulse count having a first pulse width and a first programming voltage. Then, programming a second group of multi-level memory cells with the second programming level with a second programming pulse count having a second pulse width and a second programming voltage. Then programming a third group of multi-level memory cells with the third programming level with a third programming pulse count having a third pulse width and a third programming voltage.
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Advanced Micro Devices , Inc.
Brinks Hofer Gilson & Lione
Elms Richard
Nguyen Hien
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