Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2000-08-07
2002-02-12
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S155000
Reexamination Certificate
active
06346898
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to multilevel analog to digital data converters (ADCs). More particularly, the present invention relates to multilevel ADCs having dynamic element matching in a reference data path.
2. Description of the Prior Art
Multiple level, or multilevel, analog to digital data converters (ADCs), are useful in high speed, high power applications, for example for converting an input analog signal into a digital signal prior to digital signal processing. One type of ADC for high speed applications is based upon a delta sigma modulator. Delta sigma modulation incorporates a noise-shaping technique whereby the noise of a quantizer operating at a frequency much greater than the bandwidth is moved to frequencies not of interest in the output signal. A filter after the quantizer removes the out of band noise. The resulting system synthesizes a high resolution data converter, but is constructed from low resolution building blocks. A good overview of the theory of delta sigma modulation is given in “Delta-Sigma Data Converters,” by Norsworthy, Schreier and Temes, IEEE Press, 1997. Another useful reference is “A 2.5MSample/s Multi-bit DS CMOS ADC with 95 dB SNR” by Geerts et al, ISSCC 2000/Paper WA 20.2, Feb. 9, 2000.
FIG. 1
shows a conventional multilevel delta sigma ADC
100
. A delta sigma ADC generally comprises a noise shaping filter element
101
which feeds into a quantizer
102
, the output of which, signal
106
, is the input to digital filter
109
and is also fed through a digital to analog converter
104
in a feedback loop to the noise shaping filter. The output of DAC
104
is combined with input signal
102
by analog summer
105
. In a delta sigma converter, there are three major factors which contribute to dynamic range, the order of the loop (generally the number of cascaded integrators), the number of levels of the quantizer, and the over sample ratio. In the case of an A/D converter, the noise shaping filter integrators are time sampled analog, usually switched capacitor, and the output is a digital bit stream to a digital decimation filter
109
, which separates out the desired band of interest
110
and passes it along for digital signal processing. Filter
101
is normally a low pass filter, although a bandpass filter is used for some applications. Quantizer
102
is often referred to as a flash A/D converter, and is typically designed from an array of comparators.
In practice, delta sigma modulators are generally at least second order, because higher order modulators better reduce noise in the signal band, due to improved filtering functions. Thus, the resulting signal to noise ratio is better. Second order delta sigma modulators are relatively stable, and easy to design. U.S. Pat. No. 5,392,042 describes how to build high order modulators for higher precision. U.S. Pat. No. 5,461,381 provides a good reference on implementation details of switched capacitor sigma delta converters.
One technique for better matching the DAC levels in the feedback to the quantizer levels in the main signal path is shown in
FIG. 2
(Prior Art). A dynamic element matching (DEM) block
202
and a switch block
204
are placed between the comparators of quantizer
102
and DAC array
104
. An example of DEM block
202
circuitry is shown in
FIG. 3
(Prior Art). DEM block
202
and switch block
204
shape the usage of the elements in DAC array
104
. For example, the DEM can be designed to ensure that all elements are used the same proportion of the time. Note, however, that the use of DEM circuitry
202
and switch circuitry
204
in the feedback path adds delay in the feedback, the most delay sensitive part of the ADC. This is important when high speed operation is desired. In addition, the quantizer is sensitive to errors due to the offset error of the comparators. This becomes more of a problem at low oversample ratios, typical of high speed operation.
FIG. 3
(Prior Art) shows one possible configuration of DEM
202
. For more detail, refer to “Delta-Sigma Data Converters,” by Norsworthy, Schreier and Temes, IEEE Press, 1997, pp. 260-264. Quantized signal
106
from multilevel quantizer
102
feeds vector quantizer
302
, which provides selection vector
312
(in this case signal
208
), a collection of bits used to selectively enable switches
204
Switches
204
route the selection signals to the proper DAC elements. Signal
312
also feeds into an error feedback structure comprising adders
304
and
310
, filter
306
(for normalizing the transfer function of DEM logic
202
, as vector quantizer has a transfer function of H
2
).Block
308
keeps all of the signal values in range, as is required for finite precision arithmetic. The operation of the DEM can be summed up as: Given a number
302
m between 0 and n, where n is the number of total elements, find the most “needy” m of the n elements, and use them at this time. Update the amount of “need” based on that usage in time for the next sample. For a first order DEM, “need” is based on the total usage of each element, the most needy is the element than has been used the least. For a second order DEM, the timing of the use is also taken into account.
The disadvantage of DEM/switch circuitry
202
and
204
is that it is in a signal path (in this case the feedback path) and therefore adds delay to the signal. This is undesirable in high speed operation.
A need remains in the art for a low power multilevel ADC with sufficient signal to noise ratio and dynamic range at high speed operation.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a low power multilevel ADC with sufficient signal to noise ratio and dynamic range at high speed operation. This object is accomplished by moving dynamic element matching function from a signal path of the delta sigma modulator to a reference signal path.
A delta sigma analog to digital converter (ADC) has a noise shaping filter element feeding a multilevel quantizer which provides an output signal and a feedback signal to a digital to analog converter (DAC) feeding back to the direct signal path. The multilevel quantizer includes dynamic element matching (DEM) circuitry to shape the usage of the quantizer comparators.
The DEM circuitry is moved to a reference path (not part of the signal path) in order to remove the time delay effect. Preferably, the DEM circuitry switches the reference voltages applied to the comparators in the multilevel quantizer. This results in comparator offset error being shaped.
REFERENCES:
patent: 5030954 (1991-07-01), Ribner
patent: 5305004 (1994-04-01), Fattaruso
patent: 6211805 (2001-04-01), Yu
Audio Logic, Inc.
Bales Jennifer L.
Macheledt Bales LLP
Williams Howard L.
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