Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-09-18
2003-10-07
Talbott, David L. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S264000, C361S780000, C361S794000, C361S795000
Reexamination Certificate
active
06630627
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a printed (wiring) substrate or board and, in particular, to a multilayered wiring substrate or board having a plurality of multilayered wiring layers. The invention involves a technique of improving the difference in propagation delay time (hereinafter also referred to simply as “delay time”) between signals propagating along a plurality of wirings that form the respective wiring layers.
2. Description of the Background Art
FIG. 15
shows appearances of a conventional memory module
200
P (i.e., its top plan view and side view). In
FIG. 15
, the illustration of detailed wiring is omitted.
Referring to
FIG. 15
, in the memory module
200
P a plurality of (nine in the figure) DRAMs (Dynamic Random Access Memory)
51
are mounted on a conventional multilayered wiring substrate
100
P. The substrate
100
P is provided with a plurality of external terminals
60
, through which sending and/or receiving of signals and supply of power are performed between the DRAMs
51
and an external system or external circuit (not shown).
FIG. 16
is a schematic longitudinal section of the multilayered wiring substrate
100
P taken along the line A—A of FIG.
15
. The substrate
100
P has six multilayered wiring layers, and wirings that form their respective wiring layers are isolated by an insulating material
2
, such as glass epoxy material. Specifically, signal wiring groups
31
and
32
, each forming a signal wiring layer, are disposed on both surfaces (main surfaces) of the multilayered wiring substrate
100
P, respectively. Signal wiring groups
33
and
34
, each forming a signal wiring layer, and a ground wiring (layer)
35
, and a power supply wiring (layer)
36
are disposed inside the multilayered wiring substrate
100
P. The signal wiring groups
31
to
34
are used for transferring, for example, an address signal relative to the operation of the DRAM
51
. The ground wiring
35
and power supply wiring
36
are used for supplying a ground potential and a power supply potential to a ground terminal and a power supply terminal of the DRAM
51
, respectively.
FIG. 17
is a schematic top plan view of a signal wiring layer formed from a signal wiring group
31
, as an example of wiring layers. As shown in
FIG. 17
, the signal wiring group
31
is composed of n strip-like signal wirings
31
a
to
31
n
which transfer, for example, an address signal of the DRAM
51
. The signal wirings
31
a
to
31
n
are disposed in this order, so as to be parallel with one another.
In general, the signal wirings that form the signal wiring groups
31
and
32
on the surface of the multilayered wiring substrate
100
P, are composed of a copper foil having a thickness of about 20 &mgr;m, and a copper plating film that has a thickness of about 20 microns and is disposed on the copper foil surface. The signal wirings that form the signal wiring groups
33
and
34
in the multilayered wiring substrate
100
P, are composed of a copper foil having a thickness of about 40 &mgr;m. The signal wirings that form the signal wiring groups
31
to
34
have a width of about 100 to 200 &mgr;m, and the wiring interval of a wiring pattern is about 100 to 200 &mgr;m. On the other hand, the ground wiring
35
and power supply wiring
36
are composed of a plane copper foil having a thickness of about 40 &mgr;m. The length of the signal wirings that form the signal wiring groups
31
to
34
is about the same as the lateral width of the memory module
200
P (i.e., the dimension in right-to-left direction in FIG.
15
), and it is usually about ten and several centimeters.
FIG. 18
is a schematic longitudinal section of the multilayered wiring substrate
100
P or memory module
200
P taken along the line B—B of FIG.
15
. As shown in
FIG. 18
, there is formed a through hole
40
extending through in the direction of thickness of the multilayered wiring substrate
100
P. The through hole
40
has a diameter of about 250 &mgr;m, and is bored by means such as a drill. A conductive layer
41
having a thickness of about 20 &mgr;m is formed on the inner wall or side wall
40
S of the through hole
40
. The conductive layer
41
is formed at the same time that the signal wiring groups
31
and
32
on the surface of the multilayered wiring substrate
100
P are formed by copper plating. Referring again to
FIG. 17
, through holes
40
ab
to
40
mn
are interposed among the signal wirings
31
a
to
31
n.
The through hole
40
and conductive layer
41
establish a connection between predetermined layers selected from the wiring layers formed from the signal wiring groups
31
to
34
, the ground wiring layer
35
, and the power supply wiring layer
36
. For instance, as shown in
FIG. 18
, the wiring layers made by the signal wiring groups
33
and
34
, respectively, are connected to the wiring layer made by the signal wiring group
31
. The pad of one signal wiring in the signal wiring group
31
is connected via a solder
52
to an external lead
51
a
of the DRAM
51
. Thereby, the DRAM
51
is connected to the wiring layers made by the signal wiring groups
33
and
34
, or to each signal wiring.
The timing that the DRAM
51
receives an address signal SA will be described by referring to
FIG. 19
, which illustrates timing charts of a clock signal CL and address signal SA. The DRAM
51
receives the address signal SA at a rise (or fall) t
0
of the clock signal CL as a reference time. In order that the address signal SA is surely received and the internal circuit of the DRAM
51
is operated stably, a set up time T
1
and hold time T
2
, each having a predetermined period of time, are provided before and after time t
0
. For achieving high speed and stable operation of the DRAM
51
, it is preferable to provide a greater operation margin to the set up time T
1
and to the hold time T
2
.
When a plurality of address signals SA are transferred on different wirings, it is desirable that all the address signals SA propagate simultaneously on the multilayered wiring substrate
100
P, and that the DRAM
51
receives them at the same time. By establishing this transfer condition, the above-mentioned margin can be set at a large value, and a high operational stability of the DRAM
51
is obtainable even at high speed operation.
However, the conventional memory module
200
P has the following problems in signal propagation. Description will now be made by taking, as an example, a wiring layer made by the above-mentioned signal wiring group
31
. The same is true for other wiring layers.
It is well known that when a plurality of wirings are disposed in close proximity, these wirings are capacitively coupled via the capacitance (or capacitor) component formed between the wirings. This condition will be described by referring to
FIG. 20
, which is a schematic longitudinal section of the multilayered wiring substrate
100
P taken along the line CP—CP of FIG.
17
. As shown in
FIG. 20
, all the signal wirings
31
a
to
31
n
can be schematically illustrated as being in a capacitive coupling in series via a capacitance (or capacitor) CSW between two adjacent signal wirings.
Likewise, when the through holes
40
ab
to
40
mn
are interposed among the signal wirings
31
a
to
31
n
, as shown in
FIG. 17
, all the signal wirings
31
a
to
31
n
and all the through holes
40
ab
to
40
mn
(specifically, all the conductive layers
41
ab
to
41
mn
) can be illustrated as shown in
FIG. 21
, which is a schematic longitudinal section taken along the line DP—DP of FIG.
17
. That is, all the signal wirings
31
a
to
31
n
and all the conductive layers
41
ab
to
41
mn
are capacitively coupled in series via a capacitance (or capacitor) CST between one signal wiring and the conductive layer of one through hole.
Referring again to
FIG. 17
, one signal wiring and one through hole are disposed on both sides of the signal wirings
31
b
to
31
m
except for the outermost signal wirings
31
a
and
31
n
. Whereas one signal wiring and one through hole
Alcalá José H.
Talbott David L.
LandOfFree
Multilayered wiring substrate with dummy wirings in parallel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multilayered wiring substrate with dummy wirings in parallel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayered wiring substrate with dummy wirings in parallel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3141593