Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2001-06-27
2002-02-26
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S668000, C257S700000, C257S680000, C257S693000, C257S697000
Reexamination Certificate
active
06351026
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a multilayered wiring structure used in a hybrid integrated circuit or the like in which a plurality of integrated circuits are mounted, and a method of manufacturing the same.
In recent years, an increase in integration degree and operation speed of LSIs is remarkably high, and multi-pin chips that operate at a clock frequency of 100 MHz or more become commercially available. In a single chip-mounted package of such a high-speed chip, a delay in signal transmitted between the package and the printed circuit board is large, and the influence of parasitic capacitance or inductance of the package cannot be neglected in system design. Signal delay caused by the influence of the parasitic capacitance and inductance interferes with an increase in operation speed of the entire system.
In order to solve this signal delay, a technique is available with which chips are arranged as close as possible to each other to form a hybrid integrated circuit (multi-chip module: MCM). With the MCM, signal delay between chips caused by the package can be decreased, and the high operation speed of a single chip can be obtained even in a system composed of a plurality of chips.
FIG. 4
shows the arrangement of the MCM. The arrangement of the MCM will be described. A lower wiring layer
503
is formed on a die pad
501
a
on a lead frame
501
through an insulating layer
502
, and an upper wiring layer
505
is formed on the lower wiring layer
503
through an interlevel insulating layer
504
. An integrated circuit chip
506
and a resistor chip
507
are mounted at predetermined positions on the upper wiring layer
505
. The integrated circuit chip
506
is connected to a predetermined portion of the upper wiring layer
505
with a wire
508
. Predetermined portions of the upper wiring layer
505
and leads
501
b
are connected to each other with wires
508
a
. The resultant lead frame
501
is encapsulated with a molding resin
509
with the distal ends of the leads
501
b
being exposed.
The insulating layer
502
and interlevel insulating layer
504
described above are made of polyimide or the like, and the respective wiring layers are formed by patterning a conductor film formed on the insulating layer
502
and interlevel insulating layer
504
by vapor deposition or sputtering. The respective wiring layers are connected to each other through via holes
510
.
The via holes
510
described above are roughly classified into two types, as shown in
FIGS. 5A and 5B
. The first type is called a stagger via hole type. According to this type, as shown in
FIG. 5A
, a via hole
603
to be connected to a lower wiring layer
601
is formed to continue to a wiring layer
604
through a hole (via hole) formed in an interlevel insulating layer
602
formed on the lower wiring layer
601
. The stagger via hole is fabricated simultaneously with formation of the wiring material of the wiring layer
604
.
The second type is called a filled via hole type, in which a filling layer is formed to fill a via hole. According to this type, as shown in
FIG. 5B
, a filling layer
603
a
is formed to fill a via hole formed in an interlevel insulating layer
602
formed on a lower wiring layer
601
, and a wiring layer
604
is formed to be connected to the filling layer
603
a
. The filling layer
603
a
constituting this filled via hole is fabricated by, e.g., plating.
Since the stagger via hole is fabricated by a process such as vapor deposition or sputtering as described above, it is not suitable when forming via holes to overlap in the vertical direction. Due to this defect, the filled via hole formed by filling is superior.
Formation of a filled via hole will be briefly described. As shown in
FIG. 6A
, wiring layers
702
and
703
are formed on a substrate
701
. As shown in
FIG. 6B
, an insulating layer
704
and a metal layer
705
respectively made of polyimide and a copper foil are formed to cover the wiring layers
702
and
703
on the substrate
701
.
The resultant structure is processed by using a resist pattern as a mask, thus forming openings at predetermined regions of the metal layer
705
. As shown in
FIG. 6C
, a metal pattern
705
a
is formed. The insulating layer
704
is etched by using the metal pattern
705
a
as a mask to form via holes
706
and
707
. The resist pattern may be removed prior to formation of the via holes or during formation of the via holes simultaneously.
Copper is deposited on the wiring layers
702
and
703
exposed to the bottoms of the via holes
706
and
707
in accordance with electroplating using the wiring layers
702
and
703
as one electrode (cathode), to fill the via holes
706
and
707
with plated copper. When the surface of the copper portion growing by plating reaches the opening ends of the via holes
706
and
707
, the upper end of the copper portion growing by plating comes in contact with the ends of the holes of the metal pattern
705
a
. When the copper portion growing by plating comes in contact with the metal pattern
705
a
, the metal pattern
705
a
becomes the common electrodeposition surface to grow copper. As shown in
FIG. 6D
, The via
706
and
707
are filled with filling layers
708
and
709
, so that a copper plating film
710
is formed on the metal pattern
705
a.
When filling the via holes
706
and
707
with copper by electroplating, if the upper end of the copper portion growing by plating comes into contact with the ends of the holes of the metal pattern
705
a
, abnormal plating growth occurs at these contact portions. Accordingly, the copper plating film
710
forms projecting portions
710
a
at the ends of the holes of the metal pattern
705
a
. This leads to a nonuniformity in the surface, which is a problem. Therefore, the projecting portions
710
a
are removed by polishing or the like to planarize the surface of the copper plating film
710
, as shown in FIG.
6
E.
The metal pattern
705
a
and copper plating film
710
are processed and upper wiring layers
711
and
712
are formed, as shown in FIG.
6
F. As a result, the wiring layers
702
and
703
are connected to the upper wiring layers
711
and
712
through the filling layers
708
and
709
, respectively. The upper wiring layers
711
and
712
are continuous to the filling layers
708
and
709
as they are formed simultaneously with the filling layers
708
and
709
by copper plating growth. The connection state between the filling layers
708
and
709
and the upper wiring layers
711
and
712
is much more reliable than that obtained when the filling layers
708
and
709
and the upper wiring layers
711
and
712
are formed separately.
Conventionally, however, as described above, abnormal plating growth causes a projecting portion
710
(dog bone phenomenon). Polishing must be performed to planarize the projecting portion.
Generally, polishing requires a very large amount of know-how, and polishing itself decreases the yield. The higher the degree of micropatterning, the cleaner the atmosphere where formation of a multilayered wiring structure is performed must be. However, polishing is a major factor that degrades cleanliness.
In fine, conventionally, since polishing is required to form filling layers, the yield of the multilayered wiring structure is degraded. If filling layers and wiring layers are simply formed separately without using polishing, unevenness or the like occurs due to the dog bone phenomenon, and the filling layers and the wiring layer cannot be connected to each other reliably.
SUMMARY OF THE INVENTION
It is, therefore, a principal object of the present invention to improve the reliability in connection between the filling layer and wiring layer of a multilayered wiring structure without using a process such as polishing that decreases the yield.
In order to achieve the above object, according to the present invention, there is provided a multilayered wiring structure comprising a first wiring layer formed on a substrate through a first insulating layer, a second
Hirasawa Koki
Ono Teruo
Anya Igwe U.
McGinn&Gibb,PLLC
Smith Matthew
LandOfFree
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