Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-02-23
2002-11-19
Martin, David S. (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S720000, C361S748000, C361S799000, C361S777000, C361S778000, C174S250000, C174S261000, C257S776000, C333S246000
Reexamination Certificate
active
06483714
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multilayered wiring board for use in an electronic circuit board or the like, and more particularly to a wiring structure of a multilayered wiring board on which a high speed operating semiconductor device is mounted.
2. Description of the Related Art
Conventionally, in the fabrication of a multilayered wiring board used as an electronic circuit board or the like for mounting thereon an electronic component including a semiconductor device such as a semiconductor integrated circuit device, interconnection conductors for internal wiring are formed by depositing layers of interconnections made of a high melting point metal such as tungsten (W), with an insulating layers made of a ceramic such as alumina formed between them.
In the conventional multilayered wiring board, of the interconnection conductors signal conductors are usually formed in a stripline structure, and above and below each layer of signal conductors is formed a large-area ground layer or power supply layer of the so-called solid pattern, with an insulating layer interposed therebetween.
With increasing speed of electrical signals handled by multilayered wiring boards, it has also been practiced to fabricate high-density, high-functionality multilayered wiring boards that can accommodate the high speed operation of semiconductor devices; that is, in the fabrication of such multilayered wiring boards, an insulating layer is formed using a polyimide resin or epoxy resin having a relatively low dielectric constant of 3.5 to 5 in place of an alumina ceramic whose dielectric constant is about 10, and an internal wiring conductor layer of copper is deposited on the insulating layer by thin film technology using vapor phase deposition such as evaporation or sputtering, and then forming microscopic conductor patterns by photolithography, the process being repeated to form multiple layers alternating between insulators and conductors.
On the other hand, for internal wiring structure within a multilayered wiring board, in order to reduce the impedance of wiring and cross talk between signal conductors and to achieve high density wiring, there has been proposed a wiring structure in which an array of parallel conductors is formed on the upper surface of each insulating layer and a plurality of such layers are stacked one on top of another with designated conductors electrically interconnected between the layers using through conductors such as via hole conductors or through hole conductors.
For example, Japanese Unexamined Patent Publication JP-A 63-129655 (1988) discloses a multilayer wiring structure in which a first conductive layer, having a plurality of first signal lines extending in a first direction and first power lines formed alternately with the first signal lines, and a second conductive layer, having a plurality of second signal lines extending in a second direction orthogonal to the first direction and second power lines formed alternately with the first signal lines, are formed in alternating fashion with an insulating layer interposed therebetween, wherein first and second power lines receiving a corresponding voltage are interconnected. According to this structure, it becomes possible to increase packing density, reduce power consumption, and increase operating speed by making effective use of the chip area of the semiconductor chips mounted thereon.
Further, Japanese Unexamined Patent Publication JP-A 1-96953 (1989) discloses a wiring structure comprising a plurality of sets of wiring planes, wherein each of the sets of wiring planes includes at least first and second wiring planes, each of the wiring planes supporting conductive wiring oriented in a principal wiring direction and further supporting a plurality of connection sites arranged at intersections of orthogonal lines, the principal direction of wiring on the first wiring plane lying at an acute angle to the principal direction of wiring on the second wiring plane. According to this structure, wiring length can be reduced, optimized, or minimized using one or several sets of standardized wiring planes.
Also, Japanese Unexamined Patent Publication JP-A 5-343601 (1993) discloses a connection system for integrated circuits, wherein conductor (wiring conductors) layers comprising no more than two layers of parallel conductor patterns are formed one on top of another with the conductor patterns arranged at right angles to each other, some conductors on the conductor layers are used as signal conductors and the other conductors as power conductors, and the conductors on the conductor layers are interconnected in such a manner that the power conductors shield the signal conductors from each other. According to this system, since a conductor grid is formed in such a manner that each signal pattern is flanked by a pair of power supply patterns, the spacing between signal patterns can be reduced and the signal patterns running in parallel can be formed over an extended length, so that effective use is made of the carrier surface, cross talk is reduced, and S/N ratio is improved.
Further, Japanese Unexamined Patent Publication JP-A 7-94666 (1995) discloses an electrical interconnection medium comprising at least first and second interconnection layers, each of the interconnection layers comprising a plurality of parallel conductive regions, the conductive regions of the second interconnection layer being oriented orthogonally to the conductive regions of the first interconnection layer, the conductive regions of the first and second interconnection layers being electrically interconnected such that at least conductive planes are substantially interdigitated on each interconnection layer and each conductive plane appears on both interconnection layers, and such that selective conductive regions can be electrically isolated from the two conductive planes to form at least one signal path. According to this interconnection medium, the number of interconnect layers is reduced while retaining the low inductance power distribution characteristics of parallel power and ground planes, as well as the high wiring density for signal interconnect wires characteristic of photolithographic fabrication techniques.
Furthermore, Japanese Unexamined Patent Publication JP-A-9-18156 (1997) discloses a multilayer printed wiring board comprising a first layer having a first signal conductor section, a first power conductor section, and a plurality of first ground conductor sections, and a second layer formed on top of the first layer and having a second signal conductor section, a second power conductor section, and a plurality of second ground conductor sections connected one for one to the plurality of first ground conductor sections, wherein the first signal conductor section of the first layer and the second signal conductor section of the second layer are twisted, that is, orthogonal, with respect to each other. According to this structure, since the total number of wiring layers can be reduced, and since the combined conductance value and combined resistance value can be held low even if the wiring width of the ground conductor sections is reduced, high density placement of ICs and other devices becomes possible and noise caused to transmission signals can be held low. Furthermore, since noise due to the mismatch of the characteristic impedance of the signal conductor sections can be reduced because of the shield effect of the ground conductor and power conductor sections, and since the first signal conductor section and the second conductor section are twisted with respect to each other, it becomes possible to control the effects of the cross talk noise caused by the electromagnetic and capacitive couplings between the two signal conductor sections.
In the multilayered wiring boards having parallel conductor arrays as described above, appropriate conductors are selected from each parallel conductor array in the multilayered wiring board in order to electrically connect an electronic com
Kabumoto Masanao
Nabe Yoshihiro
Nomoto Masaru
Takeda Shigeto
Bui Hung
Hogan & Hartson L.L.P.
Kyocera Corporation
Martin David S.
LandOfFree
Multilayered wiring board does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multilayered wiring board, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayered wiring board will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2988105