Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-03-23
2002-08-27
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000, C174S261000, C174S262000, C361S760000, C361S761000, C361S792000, C361S803000
Reexamination Certificate
active
06441314
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a multilayered substrate for a semiconductor device. More particularly, the invention relates to a multilayered substrate formed of a plurality of sets of a conductor layer and an insulation layer, i.e., a laminate of alternate conductor and insulation layers, and having a face for mounting semiconductor element thereon and another face for external connection terminals, the face for mounting semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit. The invention also relates to a method of manufacturing such a multilayered substrate.
2. Description of the Related Art
A typical multilayered substrate for semiconductor device, which may be simply called a multilayered substrate herein, is illustrated in FIG.
19
. This multilayered substrate
100
has a core substrate
102
made of resin, and an upper layered section
106
a
and a lower layered section
106
b
provided on the respective sides of the core substrate
102
, each of the upper and lower layered sections
106
a
and
106
b
having layered wiring lines
104
of a conductor, and the wiring lines
104
of the upper and lower layered sections
106
a
and
106
b
being electrically connected through a through hole via
110
piercing through the core substrate
102
. Also in each of the upper and lower layered sections
106
a
and
106
b
, wiring lines
104
on both sides of an insulation layer of resin are electrically connected through a via
118
piercing the insulation layer.
In the outermost layer of the upper layered section
106
a
, pads
124
are provided which are electrically connected with an electrode terminal
122
of a semiconductor element
120
to be mounted on the multilayered substrate
100
. The outermost layer of the upper layered section
106
a
is covered by a solder resist
126
except for the pads
124
.
In the outermost layer of the lower layered section
106
b
, pads
130
are formed to which a solder ball
128
, as an external connection terminal, is to be bonded. The outermost layer of the lower layered section
106
b
is also covered by a solder resist
132
except for the pads
130
.
The multilayered substrate for semiconductor element shown in
FIG. 19
can be produced by a build-up process illustrated in
FIGS. 20A
to
20
F. According to the build-up process, the upper and lower layered sections
106
a
and
106
b
shown in
FIG. 19
are simultaneously formed. For this reason,
FIGS. 20A
to
20
F show only the formation of the upper layered section
106
a
, omitting the formation of the lower layered section
106
b.
In the process shown in
FIGS. 20A
to
20
F, a core substrate of resin
102
having a copper foil
100
on each side is first pierced by a means such as a drill to be provided with through holes. A copper film layer is then formed on the inside wall of the through hole by electroless plating and, as required, by subsequent electrolytic plating, to have a desired thickness and form a through hole via
110
(FIG.
20
A).
The copper foil
100
of the core substrate
102
is then subjected to a subtractive process to form wiring lines
104
and pads
105
, which are formed as part of the wiring line (FIG.
20
B). A film
106
of polyimide, which is a thermosetting resin, having one face provided with a copper foil
108
thereon is adhered to the core substrate
102
, with the face provided with the copper foil
108
being upwardly faced (FIG.
20
C). In the step of adhesion of the polyimide film
106
, a resin, such as a polyimide resin, is filled in the through hole vias
110
. The film
106
with the copper foil
108
is then pierced by a laser beam to form holes
107
for the formation of vias, the hole extending to the underlying wiring line
104
to expose the pad
105
(FIG.
20
D).
A copper layer
112
is then formed on the inside wall of each of the holes
107
to electrically connect the pad
105
of the wiring line
104
and the copper foil
108
(FIG.
20
E). The copper layer
112
is formed by covering the copper foil
108
by a resist film
114
to leave the holes
107
uncovered, as shown in
FIG. 20E
, and forming a copper film layer, having a certain thickness, only on the inside wall of each hole
107
by electroless plating, sputtering or the like and, as required, by subsequent electrolytic plating.
The resist film
114
is then removed, and the copper foil
108
is subjected to a subtractive process to form wiring lines
116
(FIG.
20
F). The wiring line
116
thus formed is electrically connected with the underlying wiring line
114
through a via
118
penetrating the resin layer
106
.
By repeating the steps illustrated in
FIGS. 20C
to
20
F, the multilayered substrate for a semiconductor, shown in
FIG. 19
, can be obtained.
Using the multilayered substrate
100
as shown in
FIG. 19
, a semiconductor element
120
having a high density can be mounted thereon. In the upper layered section
106
a
of the multilayered substrate
110
of
FIG. 19
, however, since the respective layers are successively formed upwardly from the surface of the core substrate
102
, the outermost layer, on which a semiconductor element
120
is to be mounted, is prone to have a less flat surface (i.e., a less even surface) due to accumulation of unevenness of the underlying layers. Consequently, when a semiconductor element
120
is mounted on the mounting face of the multilayered substrate of
FIG. 19
in a flip chip fashion, for example, some of electrode terminals
122
of the semiconductor element
120
may be left unconnected to the pads
124
of the outermost layer of the substrate
100
.
In a build-up process illustrated in
FIGS. 20A
to
20
F, the respective layers of the upper and lower layered sections
106
a
and
106
b
are simultaneously built up on the respective sides of the substrate, as described above, because if layers are formed only on one side of the substrate, the resultant substrate may be warped. Consequently, even if it is sufficient for a substrate to have only upper layered section, it is required to form the lower layered section to prevent the substrate from being warped, which makes the resultant substrate thicker.
SUMMARY OF THE INVENTION
An object of the invention is to provide a multilayered substrate for semiconductor element having a face for mounting semiconductor element thereon which is as even as possible, and having a thickness as small as possible.
Another object of the invention is to provide a method of manufacturing such a multilayered substrate.
The inventors have found that alternately forming wiring line layers and insulation layers successively from the side for mounting a semiconductor element to the side for external connection terminals makes it possible to produce a multilayered substrate without using a core substrate, the produced multilayered substrate having a face for mounting semiconductor element thereon which is substantially even or is as even as possible.
Thus, in one aspect, the invention provides a substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. In this multilayered substrate of
Matsuda Yuichi
Rokugawa Akio
Sasaki Masayuki
Cuneo Kamand
Patel I B
Pennie & Edmonds LLP
Shinko Electric Industries Co., Inc.
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