Multilayered semiconductor device

Details Multilayered semiconductor device Multilayered semiconductor device

2002-04-03

2004-03-30

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S753000, C257S754000, C257S755000, C257S757000

Reexamination Certificate

active

06713872

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device having a multi-layer interconnection structure and a manufacturing method thereof.
2. Description of the Background Art
FIGS. 40A
to
40
F are views illustrating a related art structure of a semiconductor device having a multi-layer interconnection structure and a manufacturing method thereof. Referring to
FIG. 40A
, reference numeral
0
designates a silicon substrate;
1
is a trench isolation region;
2
is a gate oxide film; and
3
is a gate silicon film deposited by low pressure CVD (Chemical Vapor Deposition). The gate silicon film
3
is made from polysilicon or amorphous silicon doped with an impurity such as phosphorus (P) or arsenic (As).
In
FIG. 40A
, reference numeral
4
is a silicon oxide film deposited by low pressure CVD, and
5
is a silicon nitride film deposited by low pressure CVD. The gate silicon film
3
, the silicon oxide film
4
and the silicon nitride film
5
form a gate electrode. Reference numeral
6
designates a source/drain region formed at a specific location surrounded by the trench isolation region
1
and the gate electrode composed of the films
3
to
5
. The source/drain regions
6
are elements for constituting a transistor in cooperation with the gate electrode composed of the films
3
to
5
. If the transistor is of an N-type, the source/drain region
6
is formed by implanting an impurity such as phosphorus or arsenic in the silicon substrate
0
; while, if the transistor is of a P-type, the source/drain region
6
is formed by implanting an impurity such as boron (B) in the silicon substrate
0
.
Referring to
FIG. 40B
, a silicon oxide film
300
is deposited on the silicon substrate
0
to cover the gate electrode composed of the films
3
to
5
and the source/drain regions
6
.
Referring to
FIG. 40C
, the silicon oxide film
300
is etched to form side walls
301
covering the side surfaces of the gate electrode composed of the films
3
to
5
. After formation of the side walls
301
, a doped silicon film
302
made from polysilicon or amorphous silicon doped with an impurity is deposited on the silicon substrate
0
to cover the gate electrode composed of the films
3
to
5
and the side walls
301
. The doped silicon film
302
is made from silicon doped with phosphorus or arsenic if the transistor is of the N-type and is made from silicon doped with boron if the transistor is of the P-type.
Referring to
FIG. 40D
, the doped silicon film
302
is etched in such a manner that pad layers
303
connected to the source/drain regions are formed on both sides of the gate electrode composed of the films
3
to
5
.
Referring to
FIG. 40F
, the contact hole
306
is filled with polysilicon or amorphous silicon in such a manner that the filled-in silicon is connected to the pad layers
303
, to form an interconnection layer
307
. Polysilicon or amorphous silicon, which forms the interconnection layer
307
, is doped with an impurity such as phosphorus or arsenic if the transistor is of the N-type and is doped with an impurity such as boron if the transistor is of the P-type.
In recent years, with the increased demands toward miniaturization of a semiconductor device, a dimensional allowable margin between the contact hole
306
and the gate electrode composed of the films
3
to
5
has come to be reduced. In such a situation, by use of the above-described pad layer
303
, it is possible to ensure conduction between the interconnection layer
307
and the source/drain region
6
while preventing short-circuit between the interconnection layer
307
and the gate silicon film
3
.
FIG. 41
is a cross-sectional view showing a second example of the related art semiconductor device. In
FIG. 41
, parts corresponding to those in
FIG. 40
are designated by like reference numerals and explanation thereof is omitted.
Referring to
FIG. 41
, reference numeral
308
designates a high melting point metal film made from Ti, TiN or the like;
309
is a low resistance metal film made from W or the like; and
310
is a silicide film produced by reaction between a pad layer (doped polysilicon)
303
and the high melting point metal film
308
.
An interconnection layer having a sufficiently low resistance can be formed by the high melting point metal film
308
and the low resistance metal film
309
. The contact resistance at the contact boundary between the interconnection layer and the pad layer
303
can be sufficiently suppressed and also a desirable ohmic characteristic thereat can be ensured by the presence of the silicide layer
310
interposed between the interconnection layer and the pad layer
303
. As a result, in the semiconductor device shown in
FIG. 41
, the resistance between a source/drain region
6
and the interconnection layer can be sufficiently suppressed.
FIGS. 42A
to
42
F and
FIG. 43
are sectional views illustrating a manufacturing method in which a structure for connecting a source/drain region to an interconnection layer using a pad layer (hereinafter, referred to as “pad structure”) is applied to a DRAM (Dynamic Random Access Memory) as well as a structure of the DRAM fabricated by the manufacturing method. In these figures, parts corresponding to those in
FIGS. 40A
to
40
E and
FIG. 41
are designated by like reference numerals and explanation thereof is omitted.
In the case of applying the pad structure to a DRAM, as shown in
FIG. 42A
, after formation of a silicon nitride film
5
, the wafer is subjected to oxidation treatment, to form an oxide layer on side surfaces of a gate silicon film
3
. As a result, the upper and side portions of the gate silicon film
3
are covered with a silicon oxide film
4
. Referring to
FIG. 42B
, a silicon nitride film
320
is deposited by CVD to cover the entire surface of a silicon substrate
0
. Then, the silicon nitride film
320
is selectively etched using a patterned resist film
321
as a mask, to form a contact hole
322
opened to each source/drain region
6
between adjacent gate electrodes.
Referring to
FIG. 42C
, a pad layer
323
made from doped polysilicon or amorphous silicon is formed in each contact hole
322
. In
FIG. 42C
, of the two pad layers
323
, the left one is to be connected to an interconnection layer (bit line) of the DRAM, and the right one is to be connected to a storage node (capacitor) of the DRAM.
Referring to
FIG. 42D
, a silicon oxide film
324
is deposited on the entire surface of the silicon substrate
0
in such a manner as to cover the upper portions of the pad layers
323
.
Referring to
FIG. 42E
, the silicon oxide film
324
is selectively etched using a patterned resist film
330
as a mask, to form a contact hole
331
opened to each pad layer
323
to be connected to an interconnection layer.
Referring to
FIG. 42F
, a high melting point metal film
333
made from Ti, TiN or the like is formed in such a manner as to cover the surface of the silicon oxide film
324
, the side surface of each contact hole
331
, and the surface of each pad layer
323
. Then, a low resistance metal film
334
made from W or the like is formed on the high melting point metal film
333
.
Referring to
FIG. 43
, the high melting point metal film
333
and the low resistance metal film
334
are selectively etched into a desired shape, to form an interconnection layer composed of the metal films
333
and
334
. Then, the wafer is subjected to a specific heat treatment, to form a silicide film
335
near the boundary between the high melting point metal film
333
and the pad layer
323
.
After that, a first electrode of a capacitor is formed in such a manner as to be connected to the pad layer
323
for a capacitor. Then, an insulating film and a second electrode are sequentially formed thereon. A memory cell structure of the DRAM is thus realized. In the case of applying the pad structure to the DRAM as described above, even if the dimensional m

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