Multilayered integrated circuit chip wiring arrangement

Details Multilayered integrated circuit chip wiring arrangement Multilayered integrated circuit chip wiring arrangement

1991-11-21

1994-03-22

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257760, 257776, H01L 2348

Patent

active

052967425

ABSTRACT:
An integrated circuit chip includes a substrate in which active circuits are formed, a lower layer of parallel conductors formed on the substrate, and one or more intermediate layers of insulating material on the lower-layer conductors, the intermediate layers having troughs corresponding to spaces where the lower-layer conductors are absent on the substrate and crests corresponding to spaces where the lower-layer conductors are present on the substrate. An upper layer of parallel conductors is formed on the insulative layers, the upper-layer conductors extending in a direction normal to the length of the lower-layer conductors. The upper-layer conductors have a minimum step coverage of 50%, and the lower-layer conductors have a ratio of a thickness thereof to a separation therebetween, which ratio is either equal to or greater than 0.45 or equal to or smaller than 0.25.

REFERENCES:
patent: 4594606 (1986-06-01), Goto et al.
patent: 4984060 (1991-01-01), Ohmi et al.
patent: 4996584 (1991-02-01), Young et al.
Semiconductor Devices Physics and Technology, S. M. Sze, p. 344 1985.

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