Multilayered CMP stop for flat planarization

Details Multilayered CMP stop for flat planarization Multilayered CMP stop for flat planarization

2001-11-30

2004-10-19

Rose, Robert A. (Department: 3723)

Abrading

Abrading process

Utilizing fluent abradant

C451S041000

Reexamination Certificate

active

06805614

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of chemical mechanical polishing (CMP) and more specifically to stopping layers for CMP.
BACKGROUND OF THE INVENTION
Chemical-mechanical polishing (CMP) for planarizing semiconductor wafers during fabrication is becoming more and more common. Two key areas in which CMP planarization is critical are shallow trench isolation (STI) and interconnect layers. A CMP system generally consists of a polishing pad, wafer carrier, and slurry. As a wafer carrier positions a semiconductor wafer against the polishing pad, slurry is added between the polishing pad and the wafer. The wafer, the pad, or, more typically, both are moved to planarize the surface of the wafer. CMP employs both a mechanical removal of material (due to the physical abrasion of the polishing pad and slurry particles against the surface of the wafer) and a chemical removal (etch) of material (due to the chemical components of the slurry).
The planarization uniformity for many integrated circuits is difficult to control across the entire die or wafer. This is mainly due to the topography of the wafer. Process irregularities such as pad conditioning, down force, and slurry delivery may also be a factor. Although CMP can be a timed polish, for many applications CMP uses a stop layer to determine the CMP endpoint. One such application is shallow trench isolation (STI).
STI is being widely used for isolation in large-scale integrated circuits (ICs) to isolate the active areas of transistors and other devices from each other. STI is formed prior to transistor formation. Referring to
FIG. 1A
, a pad oxide
12
and pad nitride
14
are deposited over the surface of the semiconductor
10
. The pad oxide
12
and nitride
14
are then patterned and etched to form a hard mask for the trench etch. Shallow trenches
16
are then etched into the semiconductor surface
10
. A trench liner (not shown) may be deposited on the surface of the trench
16
and the trench is filled with a dielectric material
20
, such as high density plasma (HDP) silicon dioxide. This is followed by CMP using the pad nitride
14
as a polish stop. As shown in
FIG. 1B
, various oxide step heights remain across the wafer. The delta in oxide
20
height may be on the order of 100-200 nm. The oxide step heights become more pronounced when the pad nitride
14
and pad oxide
12
are later removed.
Significant dishing and non-planarity results after CMP depending on the range of pattern densities on the chip. Despite the addition of dummy moats (active areas), the oxide step height differences over the active areas can range as high as 100-200 nm. This is most significant when a large capacitor, such as those used in test chips, are included. Such non-planarity presents formidable problems for linewidth control and overetch budgets in subsequent process steps. Reverse pattern etch-back and separate CMP monitor wafers (to monitor process parameters such as GOI-gate oxide integrity) are used to reduce non-planarity arising from a large range of pattern densities at the expense of increasing manufacturing cost. High selective CMP slurries do not eliminate dishing due to pattern density difference.
SUMMARY OF THE INVENTION
The invention comprises at least a three layer film, such as nitride/oxide
itride for a CMP stop layer. A gap filling material is polished, stopping on the first film. The first film is then stripped using an etch chemistry that is selective against removing the second film. CMP is then continued stopping on the third film.
An advantage of the invention is method of providing a more uniform polished surface.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.


REFERENCES:
patent: 5930645 (1999-07-01), Lyons et al.
patent: 6001706 (1999-12-01), Tan et al.
patent: 6391768 (2002-05-01), Lee et al.
patent: 6410403 (2002-06-01), Wu

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