Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1998-08-04
2001-03-13
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S533000, C257S536000
Reexamination Certificate
active
06201286
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 9-224281, filed on Aug. 5, 1997, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a multilayer wiring substrate which is manufactured through a firing process and holds therein passive circuit elements such as a resistive element and an inductor element, and to a method of manufacturing the same.
2. Description of the Related Art
When a thick-film resistive element is formed within multilayer wiring substrate for a hybrid integrated circuit, conventionally, as shown in
FIG. 12
, a plurality of conductive patterns
2
including a pair of resistive element terminal electrodes
2
a
are formed on an insulating substrate
1
by printing and firing steps using conductive paste. Then, a thick-film resistive element
3
is formed across the pair of the terminal electrodes
2
a
by printing and firing steps using resistive paste. The thick-film resistive element
3
and the conductive patterns
2
are covered with a protective overcoat glass (not shown).
However, in the construction described above, the terminal electrodes
2
a
and the thick-film resistive element
3
are arranged in a two-dimensional state, so that a region indicated with slant lines in
FIG. 12
becomes a dead space for the thick-film resistive element
3
. As a result, the area necessary for arranging the thick-film resistive element
3
becomes large, resulting in increase in entire area of the substrate. To solve this problem, recently, a substrate technique for forming a multilayer wiring substrate has been adopted. An example of this kind of substrate technique will be explained referring to
FIGS. 14A
to
14
D.
First, as shown in
FIG. 14A
, a plurality of conductive patterns
5
are formed on an insulating substrate
4
by printing and firing steps using conductive paste. The conductive patterns
5
includes a pair of terminal electrodes
5
a
for a resistive element. The insulating substrate
4
is made of inorganic material. Next, as shown in
FIG. 14B
, a thick-film resistive element
6
is formed to be connected to the terminal electrodes
5
a
on the insulating substrate
4
by printing and firing steps using resistive paste.
After that, as shown in
FIG. 14C
, an insulating layer
7
made of for example glass material is formed on the insulating substrate
4
to have via holes
7
a for exposing the terminal electrodes
5
a
and parts of the conductive patterns
5
. As shown in
FIG. 14D
, then, terminal electrodes
8
filling the via holes
7
a
and conductive patterns
9
disposed on the insulating layer
7
to be connected to the terminal electrodes
8
are formed by printing and firing steps using the conductive paste. Accordingly, a thick-film multilayer wiring substrate for a hybrid integrated circuit is completed. Incidentally,
FIGS. 14A
to
14
D show the process for forming the thick-film wiring substrate having a two-layer structure in a stepwise manner; however when a thick-film multilayer wiring substrate having more than three layers is manufactured, after the printing and firing steps are carried out to form the terminal electrodes
8
and the conductive patterns
9
, the steps shown in
FIGS. 14A
to
14
D are repeatedly carried out.
In the process described above, in the firing step for the insulating layer
7
, a temperature is raised to approximately 850° C.-900° C. As opposed to this, a normal temperature range of the thick-film multilayer wiring substrate is comparatively low (for example −40° C.-150° C.). Accordingly, residual stress is produced due to a difference in thermal expansion coefficient between the thick-film resistive element
6
and the insulating layer
7
.
In the conventional structure, as shown in
FIG. 13
, the thick-film resistive element
6
swells up at overlapping portions with the terminal electrodes
5
a
. Therefore, the residual stress is liable to concentrate on swelling portions A of the thick-film resistive element
6
to cause cracks. Likewise, the insulating layer
7
has portions B corresponding to the swelling portions A. The portions B of the insulating layer
7
have a thickness thinner than that of the peripheral portion thereof and slightly swell up along the swelling portions A of the thick-film resistive element
6
. Accordingly, cracks may be generated at the portions B and may grow toward the thick-film resistive element
6
. When the thick-film resistive element
6
has the cracks therein, its value of resistance deviates from the target value thereof, resulting in decrease in reliability. This kind of problem occurs in the so-called green sheet lamination method as well.
SUMMARY OF THE INVENTION
The present invention is made in view of the above problems. An object of the present invention is to reduce an entire area of a multilayer substrate. Another object of the present invention is to prevent cracks from being produced in a multilayer substrate due to residual stress generated by a firing step. Still another object of the present invention is to provide a method of manufacturing the multilayer substrate realizing the above objects.
Briefly, in a multilayer substrate of the present invention, a passive circuit element is disposed above an insulating base substrate, and an insulating member is disposed on the insulating base substrate with the passive circuit member interposed therebetween. A via hole is formed through the insulating member to expose a part of the passive circuit element and a terminal electrode is disposed in the via hole.
Accordingly, the terminal electrode is disposed on the passive circuit element without expanding from the passive circuit element in a direction parallel to the surface of the base substrate, so that the entire area of the multilayer substrate can be reduced. Because the passive circuit element has no overlapping portion partially overlapping with another layer, residual stress hardly concentrates on the passive circuit element, so that the passive circuit element is prevented from having cracks therein.
The insulating base substrate can have a base substrate and an insulating layer disposed on the substrate. In this case, the passive circuit element is disposed on the insulating layer. The insulating base substrate can be composed of a plurality of green sheets laminated with one another. In this case, the insulating member is also composed of a green sheet.
The multilayer substrate described above is manufactured by steps of: disposing a passive circuit element material at a specific portion on the insulating base substrate or on the insulating layer disposed on the base substrate; firing the passive circuit element material to form the passive circuit element; disposing an insulating material to cover the passive circuit element and to have a via hole for exposing the passive circuit element therefrom; firing the insulating material to form a thick-film insulating layer on the passive circuit element; filling the via hole with a conductive material; and firing the conductive material to form a terminal electrode in the via hole.
The thick-film insulating layer can be formed by repeating the steps of disposing and firing the insulating material. The passive circuit element may be a resistive element. In this case, preferably, a step of trimming the resistive element is performed after the steps of disposing and firing the insulating material are carried out at least one time, respectively. Accordingly, a value of resistance of the resistive element can be precisely controlled.
REFERENCES:
patent: 4285001 (1981-08-01), Gerzberg
patent: 5593722 (1997-01-01), Otani et al.
patent: 5633785 (1997-05-01), Parker et al.
patent: 5770886 (1998-06-01), Rao et al.
patent: 5847442 (1998-12-01), Mills, Jr. et al.
patent: 5891795 (1999-04-01), Arledge et al.
patent: 1-298796 (1989-12-01), None
patent: 2-288290 (1990-11-01), None
patent: 6-77660 (1994-03-01), None
paten
Denso Corporation
Meier Stephen D.
Pillsbury Madison & Sutro LLP
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