Metal fusion bonding – Process – Preplacing solid filler
Reexamination Certificate
2000-08-11
2001-12-11
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
Preplacing solid filler
C228S175000, C228S180220, C156S060000, C156S288000, C438S613000
Reexamination Certificate
active
06328201
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a multilayer wiring substrate suitable for mounting a semiconductor chip, etc., and a method for producing the same.
BACKGROUND OF THE INVENTION
Recently, with small-sizing and increasing the performance of electronic instruments, small-sizing and thinning, increasing the performance, and high reliability have been required for semiconductor devices constituting electronic instruments and multilayer print wiring substrates for mounting them. Due to those requirements, the mounting method is shifted from a pin-insertion type packing to a surface mounting type packaging. Recently, a mounting method called bare chip mounting which directly mounts a semiconductor chip on a printed substrate has been investigated. Also, with increasing the number of pins of a semiconductor chip, the necessity of using a multilayer of a substrate for mounting the semiconductor element has been increased. A method of forming a multilayer substrate is proposed, wherein a multilayer wiring substrate of a build-up system is formed by alternately piling up each insulating layer using a photosensitive resin and each conductive layer formed by plating or a vapor deposition, on one surface or both surfaces of a substrate. However, such a multilayer wiring substrate has the problems that the production steps are complicated, the number of steps is increased, the yield is low, the time of delivery is long, and the like. Also, a method of forming a multilayer substrate by forming an electrically conductive paste as projections by dispenser, etc., on one surface (copper-clad surface) of a glass and epoxy one-surface copper-clad laminate plate, laminating an adhesive sheet and a copper foil thereon, pressing the assembly, and repeating the procedure is proposed as disclosed in JP-A-8-288649 (the term “JP-A” as used herein means an “unexamined published Japanese patent application”). However, this method has problems in the reliability of connection, the connection resistance, etc. This method also has various problems that it is difficult to apply to fine circuits and also it is necessary to repeat pressing the required number of the layers for the formation of a multilayer structure, which requires increased time for the production.
On the other hand, the bare chip mounting involves adhering a silicon chip having a thermal expansion coefficient of from 3 to 4 ppm/° C. to a printed substrate having a thermal expansion coefficient of from 10 to 20 ppm/° C. directly via an adhesive. Therefore, a problem arises that a stress is applied due to the difference in the thermal expansion coefficients, thereby decreasing the connection reliability. Further, the stress causes the problem such that cracks occur in the adhesive to decrease moisture resistance. To relax such a stress, a method of, for example, attempting diffusion of the stress by decreasing a modulus of elasticity of the adhesive have been practiced. However, even by these methods, the connection reliability cannot sufficiently be ensured, and to ensure a higher connection reliability, it is necessary and indispensable to decrease the thermal expansion coefficient of the substrate itself. To overcome this problem, a multilayer wiring substrate using a Ni—Fe alloy as a plate and alternately piling up thereon each insulating layer and each wiring conductor, or a multilayer wiring substrate obtained by forming a solder pad on the surface layer of the above-described multilayer wiring substrate by a photoetching method followed by heat-pressing to integrate them in a body is proposed as disclosed in JP-A-61-212096.
However, when copper is used as the wiring electric conductor in these multilayer wiring plates, the modulus of elasticity of the copper is very large as compared with the modulus of elasticity of a polyimide resin constituting the insulating layer. Therefore, it is difficult to decrease the thermal expansion coefficient of the entire multilayer wiring plate as that of silicon constituting a semiconductor chip. Also, since a metal thin-film forming technique such as a vapor deposition method, a sputtering method, etc., is used, the productivity is low and the production cost increases. Furthermore, a solder pad is formed by a vapor deposition method or a photoetching method, so that a complicated step is required.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above circumstances.
One object of the present invention is to provide a multilayer wiring substrate which can be easily produced and has a high connection reliability.
Another object of the present invention is to provide a method for producing the multilayer wiring substrate.
According to a first embodiment of the present invention, there is provided a multilayer wiring substrate comprising a plurality of double-sided circuit substrates each comprising an insulating layer which comprises an organic high molecular weight resin having formed on both surfaces thereof a wiring conductor, the wiring conductors on both surfaces being electrically connected by a throughhole, wherein the double-sided circuit substrates are laminated through an adhesive layer in a body, holes are formed in the adhesive layer at predetermined positions of the portions which contact the wiring conductors of the two double-sided circuit substrates sandwiching the adhesive layer therebetween, a solder-made electric conductor is formed in the hole, and the wiring conductors of the two double-sided circuit substrates are electrically connected each other by the solder-made electric conductor.
According to a second embodiment of the present invention, there is provided a method of producing the multilayer wiring substrate, which comprises the steps of:
preparing a plurality of double-sided circuit substrates each comprising an insulating layer which comprises an organic high molecular weight resin having formed on both surfaces thereof wiring conductors, both the wiring conductors being electrically connected by a throughhole, and an adhesive sheet having holes at positions corresponding to the predetermined portions of the wiring conductors of the double-sided circuit substrates;
temporarily adhering the adhesive sheet to the double-sided circuit substrates in the state that the holes of the adhesive sheet are position-matched with the predetermined portions of the wiring conductors of the double-sided circuit substrates,
filling up the holes of each adhesive sheet with a solder paste and heat-melting the solder paste to form a solder bump; and
position-matching such that the wiring conductors of the double-sided circuit substrates can be electrically connected in the predetermined manner, piling up the double-sided circuit substrates, and then heat-pressing the resulting assembly to integrate the assembly in a body.
As a result of a series of investigations to obtain a multilayer wiring substrate which can be easily produced and has a high connection reliability, it has been found that a multilayer wiring substrate can be easily produced by the above-described production method, and the multilayer wiring substrate obtained has a high connection reliability. The present invention has been completed based on this finding.
According to the method of the present invention, the adhesive sheet is temporarily adhered to the double-sided circuit substrates after position-matching, a solder bump is formed in the holes formed in the adhesive sheet, and the double-sided circuit substrates are piled up with position-matching followed by heat-pressing to integrate the entire assembly in a body. Therefore, a plurality of double-sided circuit substrates can be integrated in a body by one heat-pressing. Simultaneously, regardless of the number of layers of the wiring conductors, the electric connection between the wiring conductors can be performed by the one heat-pressing. Further, through holes are formed in each double-sided circuit substrate and the wiring conductors at both surfaces of each double-sided wiring substrate are electrically connected. Th
Inoue Yasushi
Sugimoto Masakazu
Dunn Tom
McGuireWoods LLP
Nitto Denko Corporation
Stoner Kiley
LandOfFree
Multilayer wiring substrate and method for producing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multilayer wiring substrate and method for producing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayer wiring substrate and method for producing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2570809