Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2011-08-16
2011-08-16
Wagner, Jenny L. (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257SE23070, C174S261000
Reexamination Certificate
active
07999392
ABSTRACT:
A multilayer interconnection structure according to this invention is applied to a case where a plurality of interconnections are formed at a fine pitch and a via is connected to at least one of the interconnections. In the multilayer interconnection structure, a region facing the via is locally narrowed in at least the interconnection, facing the via, of the interconnections adjacent to the interconnection connected to the via.
REFERENCES:
patent: 6163067 (2000-12-01), Inohara et al.
patent: 7238619 (2007-07-01), Zhou et al.
patent: 7486525 (2009-02-01), Knickerbocker
patent: 7495340 (2009-02-01), Kim
patent: 57-050448 (1982-03-01), None
patent: 4-085933 (1992-03-01), None
patent: 2002-110644 (2002-04-01), None
patent: 2003-173013 (2003-06-01), None
patent: 2003-197738 (2003-07-01), None
patent: 2003-297920 (2003-10-01), None
patent: 2004-095902 (2004-03-01), None
patent: 2004-144975 (2004-05-01), None
patent: 1020040039593 (2004-05-01), None
Hayashi Yoshihiro
Ohtake Hiroto
Renesas Electronics Corporation
Sughrue & Mion, PLLC
Wagner Jenny L.
LandOfFree
Multilayer wiring structure, semiconductor device, pattern... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multilayer wiring structure, semiconductor device, pattern..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayer wiring structure, semiconductor device, pattern... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2644458