Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2006-12-12
2006-12-12
Brewster, William M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S760000, C257S764000, C257S774000, C257SE21584
Reexamination Certificate
active
07148572
ABSTRACT:
A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
REFERENCES:
patent: 5354712 (1994-10-01), Ho et al.
patent: 5451804 (1995-09-01), Lur et al.
patent: 5627345 (1997-05-01), Yamamoto et al.
patent: 5691572 (1997-11-01), Chung
patent: 5864179 (1999-01-01), Koyama
patent: 5904556 (1999-05-01), Suzuki et al.
patent: 5904557 (1999-05-01), Komiya et al.
patent: 5925227 (1999-07-01), Kobayashi et al.
patent: 6267122 (2001-07-01), Guldi et al.
patent: 4-296041 (1992-10-01), None
patent: 5-275426 (1993-10-01), None
patent: 7-130854 (1995-05-01), None
patent: 8-167609 (1996-06-01), None
patent: 8-191104 (1996-07-01), None
patent: 8-274101 (1996-10-01), None
“Impact of Test Structure Design on Electromigration Lifetime Measurements,” by Ting et al., Proc. of IEEE (1995), pp. 326-332.
“Stress-Induced Voiding in Stacked Tungsten Via Structure,” by Domae et al., Proc. of IEEE, 98CH36173 36th Annual International Reliability Physics Symposium, Reno, Nevada (1998), pp. 318-323.
Domae Shinichi
Kato Yoshiaki
Masuda Hiroshi
Yano Kousaku
LandOfFree
Multilayer wiring structure of semiconductor device, method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multilayer wiring structure of semiconductor device, method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayer wiring structure of semiconductor device, method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3673460