Active solid-state devices (e.g. – transistors – solid-state diode – Miscellaneous
Reexamination Certificate
2001-01-17
2003-06-17
Chaudhuri, Olik (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Miscellaneous
C257S773000, C257S774000, C257S775000, C438S622000
Reexamination Certificate
active
06580176
ABSTRACT:
BACKGROUND OF THE INVENTION
Recent miniaturization of the wirings in ULSIs disadvantageously contributes to a reduction in reliability of the wirings. In particular, due to a development in multilamination of wirings, there is increasingly used a so-called stacked structure in which upper and lower plugs made of a high-melting-point metal such as W (tungsten), TiN or the like and its compound, are respectively disposed, as opposite to each other, on and under a wiring. In such a stacked structure, that portion of the wiring held by and between the plugs is disadvantageously weak in reliability.
To enhance the wiring reliability, a first method of prior art is for example arranged to prevent the stress migration that stress from a protective layer disconnects wirings. More specifically, a wiring layer large in grain size is formed in a region in which a major portion of the electric current flows, and a wiring layer small in grain size is formed at a position to which stress is relatively readily applied, such as a surrounding of the wiring (in particular, lateral wall or upper end portion)(See Japanese Patent Laid-Open Publication No. 5-275426).
According to a second method of prior art, there is proposed a stacked structure in which the width of each wiring is smaller than the width of the lower-layer-side connection hole and in which the bottom of the upper-layer-side connection hole extends into the lower-layer-side connection hole such that the wiring is reinforced as if entirely surrounded (See Japanese Patent Laid-Open Publication No. 8-167609).
According to the first method of prior art, however, the wiring is formed by forming a wiring layer small in grain size at a lateral wall of a wiring layer large in grain size. This excessively increases the width of the wiring and is therefore not suitable for miniaturization.
According to the second method of prior art, the width of each of the upper- and lower-layer-side connection holes is inevitably larger than the width of the wiring. This is neither suitable for miniaturization. Further, no consideration has been taken for stress from a high-melting point metal or its compound which surrounds the wiring.
SUMMARY OF THE INVENTION
In a multilayer wiring structure of a semiconductor device having a stacked structure, the present invention is proposed with the object of restraining a wiring from being lowered in reliability, particularly, due to stress applied to that portion of the wiring held by and between upper- and lower-layer-side plugs
Further, the present invention provides a semiconductor device which is to be used for reliability evaluation and which has a test pattern capable of detecting, with high sensitivity, a connection failure in a stacked structure.
More specifically, a multilayer wiring structure of a semiconductor device according to the present invention comprises: a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein when viewed in the direction of vertical line of the substrate surface, the distance between center of contact surface between the upper plug and the wiring, and center of contact surface between the lower plug and the wiring is about ⅔ or more of the diameter of each of the upper and lower plugs.
Further, a multilayer wiring structure of a semiconductor device according to the present invention comprises; a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the upper plug is inserted from the top surface of the one wiring layer to a depth of about ⅓ or more of the thickness thereof, the one wiring layer has a part projecting into lower side and being in contact with said lower plug, and the height of the projecting part from the undersurface of the one wiring layer is about ⅓ or less of the diameter of each of the lower plugs.
Further, a multilayer wiring structure of a semiconductor device according to the present invention comprises: a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the wiring has no grain boundary in the region between the opposite upper and lower plugs.
Further, a multilayer wiring structure of a semiconductor device according to the present invention comprises; a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the difference in thermal expansion coefficient between the material of the wiring and the material of at least one of the upper and lower plugs is so small that no void may be generated in the region of the wiring between the opposite upper and lower plugs.
A multilayer wiring structure of a semiconductor device according to the present invention comprises; a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the one wiring layer has a layer of a high-melting-point metal or an alloy of high-melting-point metal on the top surface thereof, and the wiring is in contact with the upper plug through the layer of a high-melting-point metal or an alloy of high-melting-point metal.
Further, a multilayer wiring structure of a semiconductor device according to the present invention comprises; a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the one wiring layer has a layer of a high-melting-point metal on the undersurface thereof, and said layer of a high-melting-point metal has a thickness of not greater than 10 nm or not less than 80 nm.
Further, a method of producing a multilayer wiring structure of a semiconductor device according to the present invention comprises; a step of forming a first opening in a first insulating layer formed on a substrate and forming a lower plug in the first opening; a step of forming a wiring on the first insulating layer and the lower plug; and a step of forming a second insulating layer on the wiring, and forming, in the second insulating layer and the wiring, a second opening opposite to the first opening and with a depth of about ⅓ or more of the thickness of the wiring, and forming an upper plug in the second opening; at the lower plug forming step, a CMP or etching-back method being used such that the distance between top surface of the lower plug and top surface of the first insulating layer, is about ⅓ or less of the diameter of each of the upper and lower plugs.
Further, a method of producing a multilayer wiring structure of a semiconductor device according to the present invention comprises: a step of forming a first opening in a first insulating layer formed on a substrate and forming a
Domae Shinichi
Kato Yoshiaki
Masuda Hiroshi
Yano Kousaku
Brewster William M.
Chaudhuri Olik
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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