Multilayer wiring structure for memory circuit

Details Multilayer wiring structure for memory circuit Multilayer wiring structure for memory circuit

2011-01-04

2011-01-04

Fahmy, Wael M (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S775000, C257S784000, C257SE23020, C257SE23144, C438S667000

Reexamination Certificate

active

07863751

ABSTRACT:
A semiconductor integrated circuit device includes: a semiconductor substrate, on which diffusion layers are formed; and multilayered wirings stacked above the semiconductor substrate to be connected to the diffusion layers via contact plugs, wherein a first wring and a second wiring formed thereabove are connected to the diffusion layers via first contact plug(s) and second contact plugs, respectively, and the number of the second contact plugs arrayed in parallel is set to be greater than that of the first contact plug(s).

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patent: WO 03/085675 (2003-10-01), None
patent: WO 2004/084229 (2004-09-01), None
U.S. Appl. No. 12/718,374, filed Mar. 5, 2010, Okukawa et al.

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