Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-09-12
2002-12-10
Talbott, David L. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C174S262000, C174S264000, C361S746000, C361S795000, C361S812000, C428S901000
Reexamination Certificate
active
06492599
ABSTRACT:
REFERENCE TO RELATED APPLICATION
This application claims the priority right under Paris Convention of Japanese Patent Application Nos. 258545/1999 filed on Sep. 13, 1999 and 258261/2000 filed on Aug. 28, 2000, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
(i) Field of the Invention
The present invention relates to a multilayer wring board suitable as a multilayer wiring board for a wafer block contact board constituting a part of a wafer block contact board used for executing a test (inspection) of a plurality of semiconductor devices formed on a wafer in the state of a wafer in a lump, and a manufacturing method thereof and others.
(ii) Description of the Related Art
The inspection for a plurality of semiconductor devices formed on a wafer is roughly divided into a product inspection by using a probe guard (electrical characteristic test) and a burn-in test which is a reliability test carried out after the former test.
The burn-in test is one of screening tests conducted in order to eliminate a semiconductor device which has an inherent defect or a device which develops trouble depending on a time and stress due to irregularities in manufacture. It can be said that the inspection using a probe card is an electrical characteristic test of a manufactured device, whereas the burn-in test is a thermal acceleration test.
If the burn-in test adopts an usual method by which a wafer is cut into chips by dicing after the electrical characteristic test conducted for each chip by using the probe card and the burn-in test is executed with respect to each packaged chip (1-chip burn-in system), the feasibility is poor in terms of cost. Therefore, development and practical application of a wafer block contact board (burn-in board) for conducting the burn-in test of multiple semiconductor devices formed on the wafer in a lump are advanced (Japanese patent application laid-open No. 231019-1995). A wafer block burn-in system using a wafer block contact board has the high feasibility in terms of cost and is an important technique in order to realize the trend of up-to-date technology such as the pair chip shipment or pair chip onboard.
The wafer block contact board has a different demand characteristic from that of the conventional probe card in that the wafer is inspected in a lump and the board is used for a heating test, and has the high demand level. If the wafer block contact board comes into practical use, the product inspection (electrical characteristic test) which has been carried out by using the probe card in the prior art can be conducted with respect to the wafer in a lump.
FIG. 12
shows one specific example of the wafer block contact board.
As shown in
FIG. 12
, the wafer block contact board has such a structure as that a membrane ring
30
having bumps is fixed on a multilayer wiring board for a wafer block contact board (which will be referred to as a multilayer wiring board hereinafter) 10 through an anisotropic conductive rubber sheet
20
.
The membrane ring
30
having bumps bears a contact portion which directly comes into contact with a device to be inspected. In the membrane ring
30
having bumps, a bump
33
is formed on one side of a membrane
32
stretched across a ring
31
and a pad
34
is formed on the other side of the same. The bump
33
is associated with a rim of each semiconductor device (chip) on a wafer
40
or a pad formed on a center line (one chip corresponds to approximately 600 to 1000 pins and pads whose number is a product obtained by multiplying the number of pins by the number of chips are formed on the wafer) and the bumps
33
are formed at positions whose number is equal to the number of pads.
The membrane ring with bumps
30
bears a contact portion which directly comes into contact with a device to be inspected. In the membrane ring with bumps
30
, a bump
33
is formed on one side of a membrane
32
stretched across a ring
31
and a pad
34
is formed on the other side of the same. The bump
33
is associated with a rim of each semiconductor device (chip) on a wafer
40
or a pad formed on a center line (one chip corresponds to approximately 600 to 1000 pins and pads whose number is a product obtained by multiplying the number of pins by the number of chips are formed on the wafer) and the bumps
33
are formed at positions whose number is equal to the number of pads.
The multilayer wiring board
10
has on an insulating board a wring for supplying a predetermined burn-in test signal and others to each bump
33
isolated on the membrane
32
through the pad
34
. Since the wiring of the multilayer wiring board
10
is complicated, the multilayer wiring board
10
usually has a multilayer wiring structure such that a plurality of wiring layers are superimposed through an insulating film. Further, in the multilayer wiring board
10
, the insulating board having the low coefficient of thermal expansion is used in order to avoid a connection failure caused by displacement of the pad
34
on the membrane
32
due to thermal expansion.
The anisotropic conductive rubber sheet
20
is an elastic body (which consists of silicon resin and has metal particles embedded in a pad electrode portion thereof) having the conductivity only in a direction vertical to a principal surface and electrically connects a terminal (not shown) of the multilayer wiring board
10
with a pad
34
on the membrane
32
. When a convex portion of the anisotropic conductive rubber sheet
20
formed on the surface thereof is brought into contact with the pad
34
on the membrane
32
, irregularities of the surface of the semiconductor wafer
40
and unevenness of the heights of the bumps can be absorbed, and the pad on the semiconductor wafer can be assuredly connected to the bump
33
on the membrane
32
.
To each semiconductor device (chip) are formed a power supply of an integrated circuit, a ground and a pad electrode which functions as an input/output terminal (I/O terminal) for a signal (a power supply pad, a ground pad and an I/O pad) respectively, and a bump electrode of the wafer block contact board is formed and connected in one-to-one relationship with respect to all the pad electrodes of the semiconductor chip.
In the multilayer wiring board constituting a part of the above-described wafer block contact board, when the insulating film and the wiring layer are superimposed and formed on the insulating board having the coefficient of thermal expansion of not more than 10 ppm/° C. (for example, a low expansion glass board), a crack may be generated in the insulating film. This tendency becomes prominent in the insulating film of the upper layer. For example, when the wiring layer, the insulating film, the wiring layer, the insulating film and the wiring layer are alternately superimposed on the insulating board in the mentioned order, a crack is apt to be generated in the insulating film of the upper layer (the insulating film of the second layer) in particular. On the other hand, when the insulating film and the wiring layer are alternately formed on the insulating board having the coefficient of thermal expansion of not less than 10 ppm/° C. (for example, a board made of resin), a crack is not produced in the insulating film but displacement of the bump occurs when the coefficient of thermal coefficient of the wafer becomes large, which may result in the contact failure.
The cause for a crack generated in the insulating film can be considered as follows. That is, although the insulating film is generally formed by applying a liquid polymer antecedent which is then cured and highly polymerized, reduction in its cubic volume due to evaporation of a solvent or polymerization reaction generates the internal stress in the insulating film. The force produced across the insulating film (which will be referred to as a membrane stress) becomes large as a thickness of the insulating film is increased. Similarly, since the wiring of the wiring layer is partial in terms of the planar dimension, the insulating films adjacent to
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Hoya Corporation
Patel I. B.
Talbott David L.
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