Multilayer wiring board and multilayer wiring package

Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement

Reexamination Certificate

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Details

C174S050510

Reexamination Certificate

active

06372999

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board and to multilevel high speed digital packaging using the board in which interconnecting wiring between the high speed digital components or circuits is performed within the circuit board as opposed to on top of the circuit board, resulting in a reduction in circuit board thickness.
U.S. Pat. No. 5,500,804 discloses a multiple wiring media package in which the conducting wires are placed on top of the substrate and interconnections to other wires as well as other substrates are made through via holes penetrating into the circuit board.
U.S. Pat. No. 4,902,556 discloses using multilevel laminates incorporating alternating layers of epoxy and polynorbornene, where layers of copper films are deposited at the interface between the board layers and are etched to form signal lines between board layers. A brief history of laminate boards is included in the “Background Of The Invention” section of this patent.
U.S. Pat. No. 5,662,761 discloses reinforced multilevel board using a cross-ply laminate in combination with a UD fiber matrix, which has fibers overlapping and oriented in opposite directions.
High density multilevel packaging can be performed by embedding bundles of wires within a low modulus material, On the top surface of the low modulus material, RF and digital chips, such as the central processing chips or the memory circuits are soldered, or otherwise attached, to a printed circuit board layout. Within the low modulus material structure the wires criss-cross on top of each other while providing interconnections between circuitry on top of the board. This criss crossing of wires allows a significant savings in board thickness as well as surface area.
However, this method of manufacturing the multilevel digital board has some disadvantages. For example, when a digital circuit on the surface of the multilevel board needs to be replaced, the removal of the digital chip causes the embedded wires to flex and to deform because these wires are embedded in a low modulus material near the top of the board where the digital chips are located. Moreover, when the multilevel digital board is mounted down to effect chip removal or to populate the board, or at the next level of assembly, the low modulus material has a tendency to creep at the clamping or mounting sites. Moreover, the signal wires radiate electrical noise and are themselves subject to receiving external electrical noise. Moreover, the heat generated by the digital chips must conduct to the deeper layers of the board to reach a relatively dense conductive layer that will spread the heat and conduct it to mounting points. This is especially important in space applications where there is no air convection cooling.
Thus, there is a need to produce a multilevel digital circuit board that is more resistant to compressive or tensile creep, both to prevent the loss of mounting or clamping forces on the circuit board and to prevent the wires from being damaged when the digital board requires either populating for the first time with digital circuits, or refitting of the board with new digital circuits. There is also a need to provide thermally conductive layers close to the surface on which the digital chips are mounted. There is also a need to shield the signal wires from emitting or receiving electrical noise.
SUMMARY OF THE INVENTION
The present invention solves these problems by providing a multilayer wiring board which comprises a substrate having a plurality of layers of reinforced resin material, a patterned conductive layer provided on at least one major surface of the substrate, a plurality of via holes provided at least partly through the substrate, and a plurality of signal carrying wires. The signal carrying wires are provided between at least two of the layers of reinforced resin material. The signal carrying wires can be embedded in a resin layer, and the resin layer sandwiched between a pair of the layers of reinforced resin material. The reinforced resin material is preferably a fiber reinforced resin material, including but not limited to a glass fiber reinforced epoxy or polyimide material. In some applications, a constrained core, e.g., a copper/molybdenum/copper laminate, can be provided between a major surface of the substrate and the pair of reinforced resin layers sandwiching the signal carrying wires. The constrained core provides a stiffer board and can be used as a power or ground line or thermal transfer. The board can be used in a multilayer wiring package wherein a plurality of integrated circuit chips are mounted on a major surface of the board.
The present invention provides a more robust multilevel wiring board by using a new layer structure, including prepreg of fairly high modulus material, to hold the wires in place, and by burying the digital wires deep within the multilevel structure so that the flexing of the circuit board, caused when the individual digital circuits or chips are inserted or removed from the board, does not cause breakage or crushing of the digital wires. Using the board of the present invention, mounting of the high speed digital or RF hardware can be accomplished with fasteners and without cold flow. The fasteners do not loose torque; thus, retorquing is not required whenever the multilevel board is attached to the next level of assembly.


REFERENCES:
patent: 4868350 (1989-09-01), Hoffarth et al.
patent: 4882839 (1989-11-01), Okada
patent: 4902556 (1990-02-01), Benedikt
patent: 4963697 (1990-10-01), Peterson et al.
patent: 5500804 (1996-03-01), Hunsinger
patent: 5593720 (1997-01-01), Abn
patent: 5662761 (1997-09-01), Middelman
patent: 6076100 (2000-06-01), Farquhar et al.
patent: 6096411 (2000-08-01), Nakatani et al.
patent: 6121553 (2000-09-01), Shinada et al.
patent: 6175087 (2001-01-01), Keesler et al.
patent: 6248958 (2001-06-01), McClure et al.
GE Electromaterials Web Page Excerpts.

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