Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-07-02
2001-10-16
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C257S698000, C361S760000, C361S803000
Reexamination Certificate
active
06303877
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a multilayer thin-film wiring board, and particularly relates to a multilayer thin-film wiring board provided with a via for interlayer connection.
2. Description of the Related Art
Recently, multilayer thin-film wiring boards, which can provide a high-density wiring, are coming into actual use. Such a multilayer thin-film wiring board may be a so-called MCM (Multi-Chip-Module) board, which may be applied to an electronic device such as a computer. The multilayer thin-film wiring board is formed such that insulating layers and wiring layers are laminated.
A very thin insulating layer, usually formed of polyimide, maybe formed using a spin-coat technique. A wiring board having a high-density pattern may be formed by sputtering and by etching using a high-sensitivity resist.
The multilayer thin-film wiring board has a structure such that terminals (signal, power supply and ground) of electronic components such as LSI chips mounted on the surface of the board and input/output pins are respectively connected to their intended layers through a via, so as to enable a wiring and a power supply between components.
Recently, flip-chip mounting using solder bumps is widely employed, in order to deal with an increasing number of terminals resulting from LSI chips having ever higher densities. Further, heat dissipation from LSI chips mounted on the multilayer thin-film wiring board is increasing. Therefore, there is a need for a multilayer thin-film wiring board which can be used with an LSI chip having a greater number of terminals and which has good heat dissipation characteristics.
FIG. 1
is an enlarged cross-sectional diagram showing an interlayer connection via
20
provided in a multilayer thin-film wiring board
2
of the related art.
As shown in
FIG. 1
, the multilayer thin-film wiring board
2
includes a ceramic base
4
, first to sixth wiring layers
6
,
8
,
10
,
12
,
14
and
16
(respectively), an interlayer insulating layer
18
and an interlayer connection via
20
.
FIG. 1
shows an example where a solder bump
22
is joined to an upper part of the interlayer connection via
20
.
The first to sixth wiring layers
6
,
8
,
10
,
12
,
14
and
16
are laminated on the ceramic base
4
such that the layers
6
,
8
,
10
,
12
,
14
and
16
, are separated by the interlayer insulating layer
18
. The first wiring layer
6
is a ground layer, the second wiring layer
8
is a power supply layer, the third, forth and fifth wiring layers
10
,
12
and
14
, respectively are signal layers, and the sixth wiring layer
16
is a surface layer. Each of those wiring layers
6
,
8
,
10
,
12
,
14
and
16
is insulated from each other by being laminated together with the interlayer insulating layer
18
.
The interlayer insulating layer
18
is not provided at a position where the interlayer connection via
20
is formed. Therefore, the wiring layers
6
,
8
,
10
,
12
,
14
and
16
will be directly laminated, or, the first wiring layer
6
and the sixth wiring layer
16
will be electrically connected by the interlayer connection via
20
.
In the example shown in
FIG. 1
, the solder bump
22
is connected to the upper part of the sixth wiring layer
16
. This solder bump
22
acts as, for example, an external connection terminal of an LSI chip (not shown). Thus, the solder bump
22
will be electrically connected to the first wiring layer
6
by the interlayer connection via
20
. Thereby, the LSI chip and the multilayer thin-film wiring base
2
will be electrically connected.
Now, a mechanical strength of the interlayer connection via
20
which is provided in the above-described multilayer thin-film wiring board
2
will be described. The interlayer connection via
20
has a structure such that each of the wiring layers
6
,
8
,
10
,
12
,
14
and
16
are directly laminated as described above. At the lower-most part of the interlayer connection via
20
, the first wiring layer
6
is provided on the ceramic base
4
such that the total area of the first wiring layer
6
is in contact with the ceramic base
4
. The second to fifth wiring layers
8
,
10
,
12
,
14
and
16
, each having a predetermined diameter, are laminated on the first wiring layer
6
.
With the above-described structure, a difference in thermal expansion rates between the LSI chip and the ceramic base
4
may occur when heat is applied to the multilayer thin-film wiring board
2
, for example, upon mounting. The difference in thermal expansion rates is applied as a stress to the interlayer connection via
20
formed between the LSI chip and the ceramic base
4
.
As shown in the figure, the interlayer connection via
20
is supported by the interlayer insulating layer
18
which is formed of a flexible resin such as polyimide. A stress resulting from the difference in thermal expansion rates causes the interlayer connection via
20
to be displaced along the surface of the ceramic base
4
(arrow X) with a flexible deformation of the interlayer insulating layer
18
.
The first wiring layer
6
positioned at the lower-most part of the interlayer connection via
20
is in full contact with the rigid ceramic base
4
. Therefore, the first wiring layer
6
and the ceramic base
4
are positively joined with a greater mechanical strength. However, since the second wiring layer
8
forming the interlayer connection via
20
has a relatively small diameter, the above-described stress will concentrate on a position joining the second wiring layer
8
and the first wiring layer
6
(i.e., an area encircled by a dashed line indicated by an arrow A, in FIG.
1
). In the worst case, the second wiring layer
8
may peel off from the first wiring layer
6
, resulting in a disconnection. Accordingly, there is a need for a multilayer thin-film wiring board which has a sufficient reliability.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a multilayer thin-film wiring board which can satisfy the needs described above.
It is another and more specific object of the present invention to provide a multilayer thin-film wiring board which can achieve an improved reliability by preventing a disconnection of a via.
In order to achieve the above objects, a multilayer thin-film wiring board includes a plurality of branching vias provided by forming a plurality of branches in at least one of the wiring layers forming a via, the plurality of branching vias being placed along a direction of extension of the base material. The plurality of branching vias are joined to one of the plurality of wiring layers which is placed at a position closest to the base material.
In the multilayer thin-film wiring board described above, stress applied to the via is dispersed in the plurality of branching vias. Accordingly, stress applied to the via and branching vias respectively will be reduced and the via and branching vias are prevented from peeling off.
It is still another object of the present invention to provide a multilayer thin-film wiring board which can prevent the branching vias from disturbing other ones of the plurality of wiring layers, so that the plurality of wiring layers may be positioned in any order.
In order to achieve the above object, the plurality of branching vias are formed on one of the plurality of wiring layers placed at a position closer to the base material compared to a signal wiring layer of the plurality of wiring layers.
It is yet another object of the present invention to provide a multilayer thin-film wiring board which can, in a case where an element (e.g., a semiconductor chip) joined to the via produces heat, dissipate the thus-produced heat by the via and the branching vias, thus improving a heat dissipation efficiency.
In order to achieve the above object, the via is, along with the plurality of branching vias, joined to one of the plurality of the wiring layers which is placed at a position closest to the base material.
It is yet another object of the
Fukunaga Naomi
Kikuchi Shunichi
Moriizumi Kiyokazu
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Paladini Albert W.
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