Multilayer routing method and structure for semiconductor integr

Details Multilayer routing method and structure for semiconductor integr Multilayer routing method and structure for semiconductor integr

1996-05-15

1999-03-02

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

216 18, 257758, 257774, 257781, 438637, 438738, H01L 2100

Patent

active

058770917

ABSTRACT:
A constraint graph is generated by representing plural nets by using vertices and correlation in the horizontal and vertical directions among the nets by using edges. Then, clustering is conducted so that each of the vertices of the constraint graph is assigned to any one of plural layers in view of a channel height and so as to minimize the number of stacked vias. Next, routing topology is obtained on the basis of obtained clusters of the respective layers and the constraint graph, and routing patterns satisfying a design rule are obtained on the basis of the routing topology. In the clustering, the number of the stacked vias is minimized while retaining the minimum channel height in view of the final routing patterns. Accordingly, the routing patterns satisfying a desired design rule can realize a high density, resulting in a compact semiconductor integrated circuit.

REFERENCES:
IEEE Transactions On Computer-Aided Design, "Minimum-Via Topological Routing", Chi-Ping Hsu, vol. Cad-2, No. 4, pp. 235-246 (Oct. 1983).
IEEE Transactions On Computer-Aided Design, "Unconstrained Via Minimization for Topological Multilayer Routing", M. Stallmann et al., vol. 9, No. 9, pp. 970-980 (Sep. 1990).

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