Multilayer printed wiring board and multilayer printed...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C257S776000, C257S698000, C257S703000, C257S700000, C257S738000, C257S689000, C257SE23069

Reexamination Certificate

active

07368819

ABSTRACT:
In a multilayer printed wiring board having a plurality of laminated resin layers, a plurality of wiring patterns formed on the interfacial surface of the resin layers, and a plurality of lands formed on the outermost layer of the resin layers and on which the solder is provided, at least one of the wiring patterns has a plurality of openings in the form of a mesh, the size of openings of the wiring patterns in a region corresponding to the position of solder in which a stress generated in the solder provided on the lands becomes a value larger than a desired value due to thermal deformation of the semiconductor device and the multilayer printed wiring board is larger than that of openings in the other regions.

REFERENCES:
patent: 6429114 (2002-08-01), Hayama et al.
patent: 6749927 (2004-06-01), Cooray
patent: 5-343820 (1993-12-01), None
patent: 2002-100880 (2002-04-01), None

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