Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-06-29
2002-04-02
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C174S256000, C174S258000, C174S259000, C174S264000, C361S792000, C361S795000, C361S803000
Reexamination Certificate
active
06365843
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a multilayer printed wiring board having a filled-via structure in which an upper via hole is formed directly above a lower via hole.
BACKGROUND ART
The so-called build-up multilayer printed wiring board, shown in FIG.
11
(A), consists of a via hole
650
that electrically connects a lower conductor circuit
634
and an upper conductor circuit
652
to each other. The via hole
650
is formed as such that a plated film
648
is created on the inner surface of an opening
642
which is formed in an interlaminer resin insulating layer
640
. The inside portion of the plated layer
648
for forming the via hole
650
is filled with resin
660
a
in order to create an upper interlaminer resin insulating layer
660
. Therefore, if a via hole is formed above the via hole
650
as indicated by a dashed line shown in the drawing, the resin
660
a
enclosed under the plated layer
648
inhibits easy establishment of a connection between the two via holes.
Therefore, when a via hole is formed on a lower via hole, that is, when a via hole is directly connected to another via hole without any interposition of wiring in order to raise the density, a so-called filled-via structure is employed to form the multilayer printed wiring board. As shown in
FIG. 11
(I), the filled-via structure is formed such that an opening
542
in the interlaminer resin insulating layer
540
is filled with plated metal
548
. The foregoing technique has been disclosed by the applicant of the present invention in Japanese Patent Laid-Open No. 2-188992, Japanese Patent Laid-Open No. 3-3298 and Japanese Patent Laid-Open No. 7-34048.
A method of forming a via hole on another via hole will now be described with reference to FIG.
20
(B) to FIG.
11
(I).
Initially, the upper and lower surfaces of a substrate
530
having a surface on which a conductor circuit
534
has been formed are coated with resin
540
for creating a lower interlaminer resin insulating layer (see FIG.
11
(B)). An opening
542
for forming a via hole is then formed in the resin
540
(see FIG.
11
(C)). Subsequently, an electroless-plated film
544
is uniformly deposited on the surface of the substrate
530
, and then a resist film
546
is formed (see FIG.
11
(D)). This is proceeded by electrolytically-plated film
548
being deposited on a portion in which the resist film
546
is not formed. Thus, a via hole
550
and a conductor circuit
552
are formed (see FIG.
11
(E)). The resist film
546
and the electroless-plated film
544
below the resist film
546
are then separated. Subsequently, the surface of the substrate
530
is coated with resin
560
which becomes the upper interlaminer resin insulating layer (see FIG.
11
(F)). This is followed by photoetching being performed to make an opening
562
in preparation for an upper via hole in the interlaminer resin insulating layer
560
(see FIG.
11
(G)). Then, an electroless-plated film
564
is uniformly deposited on the surface of the substrate
530
, and then a resist layer
566
is formed. An electrolytically-plated film
568
is then deposited in the portion in which the resist layer
566
is not formed (see FIG.
11
M). Finally, the resist layer
566
and the electroless-plated film
564
below the resist layer are separated so that a via hole
570
and a conductor circuit
572
are formed (see FIG.
11
W).
However, the multilayer printed wiring board manufactured by the above-mentioned manufacturing method is subject to unsatisfactory reliability of the connection established between the lower via hole
550
and the upper via hole
570
. The inventor of the present invention has researched the cause of this unsatisfactory reliability, resulting in the discovery that a recess
550
a
is formed in the central portion of the via hole
550
when the electrolytically-plated film
548
is deposited in the opening
542
which is formed in the interlaminer resin insulating layer
540
, as shown in FIG.
11
(E). That is, as shown in FIG.
11
(F), when resin
560
, which will be formed into the upper interlaminer resin insulating layer, has been applied to the portion above the via hole
550
, the thickness h
1
of the resin
560
in the via recess
550
a
and thickness h
2
of the portion except for the recess
550
a
, are different from each other. Therefore, when the opening
562
for forming the via hole is created in the interlaminer resin insulating layer
560
by photoetching, a small quantity of resin
560
a
is left in the recess
550
a
as shown in FIG.
11
(G). That is, as shown in FIG.
11
(I), the resin
560
a
insulates the connection. The result of which being that, satisfactory reliability of the connection between the lower via hole
550
and the upper via hole
570
cannot be realized.
In addition to resin
560
a
in the recess
550
a
, a further occurrence has been detected that, due to the dint caused by the oxidized film, the reliability of the connection between the lower via hole
550
and the upper via hole
570
is deteriorated. That is, as shown in FIG.
11
(E), when the via hole
550
has been formed with the use of electrolytically-plated film
548
, an oxidized film is formed on the surface of the lower via hole
550
. As shown in FIG.
11
(J), the interlaminer resin insulating layer
560
, which repeats thermal contraction, imposes stress in a direction to cause the lower via hole
550
and the upper via hole
570
to be separated from each other. If an oxidized film is formed in the interface between the lower via hole
550
and the upper via hole
570
, that is, on the surface of the lower via hole
550
, the surface of the lower via hole
550
and the lower surface of the upper via hole
570
are separated from each other. As a result, the electric connection between the lower via hole
550
and the upper via hole
570
is broken.
The filled-via multilayer printed wiring board has another problem. Since recesses
550
a
and
570
a
are formed in the upper surfaces of the via holes
550
and
570
, each having the above-mentioned filled-via structure as shown in FIG.
11
(J), the smoothness of the surface of the substrate is deteriorated. Therefore, the mounting reliability that is required when an IC chip or the like is mounted is sometimes deteriorated. To improve the smoothness of the substrate, in order to overcome the above-mentioned problem, the applicant of the present invention has discovered a technique for smoothing the upper surfaces of the via holes. That is, as shown in FIG.
12
(D), the upper surfaces of the lower via hole
550
and the upper via hole
570
are flattened so that the substrate is smoothed. FIG.
12
(E) is a horizontal cross sectional view taken along line E—E shown in FIG.
12
(D), that is, FIG.
12
(E) shows a conductor layer formed on the interlaminer resin insulating layer
540
. FIG.
12
(D) is a vertical cross sectional view taken along line D—D shown in FIG.
12
(E).
However, if the upper surface of the via hole is flattened, the upper interlaminer resin insulating layer
560
above the plane layer
553
as shown in FIG.
12
(E) is raised as shown in FIG.
12
(D). Therefore, in a multilayer printed wiring board having a conductor layer in which a conductor pattern
552
and a plane layer
553
concur, it has been established that the surface of the substrate cannot be flattened.
The reason why the upper layer of the plane layer
553
is raised will now be illustrated with reference to FIGS.
22
(A),
22
(B),
22
(C) and
22
(D) showing a process for manufacturing a multilayer printed wiring board. As shown in FIG.
12
(A), both the conductor pattern
552
, and the plane layer
553
, are formed on the upper surface of the lower interlaminer resin insulating layer
540
as described above with reference to FIG.
12
(E). To form the upper interlaminer resin insulating layer as shown in FIG.
12
(B), the surface of the substrate is coated with resin
560
, which will be molded into an interlaminer resin insulating layer with the use of a roll coater or the like. However, th
Asai Motoo
Shimada Ken'ichi
Shirai Seiji
Gaffin Jeffrey
Ibiden Co. Ltd.
Patel I B
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