Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1997-07-21
2003-02-25
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C257S738000, C361S777000, C361S772000, C438S612000
Reexamination Certificate
active
06525275
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multilayer printed circuit board, and more particularly to a multilayer printed circuit board for the mounting of flip chips capable of reducing the number of wiring layers while maintaining high density packaging property on a surface of a wiring substrate.
2. Description of Related Art
In multilayer printed circuit boards for the mounting of flip chips, a group of solder pads formed by arranging many pads each provided with a solder bump is formed on a mounting surface.
In general, the solder pad group comprises pads having a structure in which sphere-shaped solder is formed on a surface of a flat and disc-shaped conductor called as a mounting pad (or land) electrically connected to a given conductor pattern of a wiring substrate through surface tension, which mounting pad is electrically connected, for example, to an external terminal for mounting a package onto a mother board or the like through given wiring drawn from the mounting pad.
In such a structure of the solder pad group, however, the solder pads located in an inner side of the solder pad group are required to electrically connect the conductor pattern connected to the mounting pad through wirings drawn from pads, which are located outside the mounting pads at a biased state, to the external terminals. Therefore, the distance between the pads located near the outer periphery of the wiring substrate is required to surely take a region corresponding to the width of the wiring and hence there is caused a problem of making the high integration of electronic components (chips) difficult.
If it is intended to attain the high integration of the electronic components (chips) in the above structure of the solder pad group, the wiring pattern is made fine and hence the frequency of failures becomes high. In the buildup wiring board forming the wiring layers on each layer, it is difficult to confirm the failure during production, so that if a failure is caused even at one place in each wiring layer, the wiring board as a final product is a failure and the good laminated material should be disposed and hence there is a problem of deterioration of production efficiency and production yield.
When multilayer printed circuit boards for mounting flip chips are particularly manufactured by the buildup method, it is necessary to attain high integration of electronic components and attain, at the same time, reduction of the wiring layer number in order to cope with mass production without reducing the production efficiency and the production yield.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to provide a multilayer printed circuit board for mounting flip chips which can realize high integration (high densification) of solder pads and reduce the number of wiring layers while maintaining high density packaging property on a surface of a wiring substrate.
The inventor has made various studies in order to achieve the above object and as a result the invention has been accomplished.
According to the invention, there is the provision of a multilayer printed wiring board comprising a core substrate, multilayer wiring layers formed thereon by alternately laminating interlaminar insulating layers and conductor circuits and a solder pad group formed by two-dimensionally arranging pads provided with solder bumps on the surface of the multilayer wiring layer, characterized in that the solder pads of the solder pad group are arranged in only a peripheral portion other than a central portion to form a frame shape and the solder pads located at the outside part among the frame-shaped solder pad group are constructed with flat pads each connected to conductor pattern on their surface and solder bumps formed on the surfaces of the flat pads, while the solder pads located at the inside part are constructed with viaholes each connected to an innerlayer flat pad group located in an innerlayer and solder bumps formed in recess portions of these viaholes.
In the multilayer printed circuit board according to the invention, it is desirable that the solder pads located at the outside part of the solder pad group are solder pads located in at least one and up to five rows viewed from the outermost periphery, and it is desirable that the interlaminar insulating layer has a roughened surface having a surface roughness of 5-15 &mgr;m.
Furthermore, it is desirable that a solder resist layer is formed on the multilayer wiring layer and an opening size of the solder resist is larger than a diameter of each of the flat pad and the viahole so as not to overlap the solder resist with the flat pad or the viahole.
Thus, the invention proposes a new structure of the solder pad group in the multilayer printed circuit board for mounting flip chips comprising the core substrate, the multilayer wiring layer formed by alternately laminating the interlaminar insulating layers and the conductor circuits and the solder pad group formed by two-dimensionally arranging pads provided with solder bumps on the surface of the multilayer wiring layer.
The term “two-dimensionally arrangement” used herein includes not only a method of arranging pads in form of network in X-Y directions as shown in FIG.
2
(
a
) but also a method of arranging pads zigzag in X-Y directions as shown in FIG.
2
(
b
). Particularly, the zigzag arrangement form is advantageous the wiring can easily be drawn out from the inside pad toward the external terminal.
The invention preferably invalues a structure in which the arrangement of the solder pad group takes a zigzag form as shown in FIG.
1
(
b
) and the solder pads located from the outermost row to a third row in the solder pad group are connected to conductor patterns on the surface of the multilayer wiring layer.
In order to draw out the wiring from the solder pad group in such a structure, it is favorable that the conductor patterns to be connected to the pads of the second and third rows are arranged so as to divide a distance between the pads of the outermost row (first row) into three equal parts and further the conductor patterns to be connected to the pads of the third row are arranged so as to divide a distance between the pad of the first row and the pad of the second row into two equal parts.
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Greenblum & Bernstein P.L.C.
Ibiden Co. Ltd.
Paladini Albert W.
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