Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Reexamination Certificate
2001-11-09
2004-07-13
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
C428S131000
Reexamination Certificate
active
06762921
ABSTRACT:
TECHNICAL FIELD
This invention relates to a multilayer printed wiring board and a method of producing the same, and more particularly it proposes a technique wherein a multilayer printed wiring board having an excellent adhesion property between electroless plated film and electrolytic plated film constituting a conductor circuit is produced by a semi-additive process without causing the peeling of a plating resist.
BACKGROUND ART
The semi-additive process is a method wherein a surface of an insulating layer is first subjected to am electroless plating, and a plating resist is formed, and an electrolytic plating is conducted by flowing current to the electroless plated film corresponding to a portion not forming the plating resist, and the electroless plated film beneath the plating resist is dissolved and removed by an etching treatment to from a conductor circuit consisting of the electroless plated film and the electrolytic plated film.
In the production method of the printed wiring board by the semi-additive process, however, when oxide film or fats and oils adheres onto the surface of the electroless plated film, if the electrolytic plated film is formed on the surface of the electroless plated film, the peeling or the like is apt to be caused at the boundary face therebetween. Particularly, the peeling is considerably caused through heat cycle, thermal shock and the like.
In the conventional semi-additive process, the surface of the electroless plated film is smooth, so that when the plating resist is formed on the surface of the electroless plated film, it is easily peeled off and there is a problem of causing short-circuit between conductor patterns.
For this end, such a problem can be solved by roughening the surface of the insulating layer and following the electroless plated film to the roughened surface.
However, if it is intended to follow the electroless plated film to the roughened surface of the insulating layer, it is required to hardly form the plated film in recess portions of the roughened surface. Because, when the plated film is simply precipitated in these recess portions, the roughened surface becomes flat.
As such an electroless plating, there is an electroless copper plating using EDTA. For example, there is Build Copper (trade name, made by Okuno Seiyaku Co., Ltd.) as disclosed in JP-A-11-68308.
When the multilayer printed wiring board is produced by using such a plating, if the diameter of theviahole is not more than 90 &mgr;m, the wiring breakage is observed in the viahole portion.
The invention is to solve the aforementioned problems inherent to the semi-additive process. A main object of the invention is to provide a multilayer printed wiring board capable of controlling the peeling produced at the boundary face between the electroless plated film and the electrolytic plated film constituting the conductor circuit by the semi-additive process through heat cycle or thermal shock to completely prevent the wiring breakage in the viahole portion.
Another object of the invention is to propose a technique capable of surely preventing the peeling of the plating resist at the production step of the printed wiring board by the semi-additive process.
DISCLOSURE OF THE INVENTION
The inventors have made various studies in order to achieve the above objects and discovered that the occurrence of such a wiring breakage is surprisingly caused due to the following mechanism.
When the electroless plated film is precipitated so as to follow to the roughened surface of the insulating layer, since such an electroless plated film hardly precipitates in the recess portions of the roughened surface, it is natural that the precipitation of the plated film hardly occurs in the inside of the viahole.
Particularly, there has been discovered a quite surprising fact that this tendency becomes conspicuous when the average diameter of the viahole is not more than 90 &mgr;m and the thickness of the electroless plated film formed on of the surface portion of the interlaminar resin insulating layer is less than 50% of the thickness of the electroless plated film at the bottom of the viahole.
At such a state, the electrolytic plated film is not precipitated or the viahole is peeled off to lower the connection reliability of the viahole portion.
Now, the inventors have further studied and found that the precipitation rate of the electroless plated film is adjusted to not more than 2 &mgr;m/hour, whereby the electroless plated film can be followed to the roughened surface of the insulating layer and at the same time the thickness of the electroless plated film at the bottom of theviahole can be adjusted to 50~100% of that of the electroless plated film formed on the interlaminar resin insulating layer surface and as a result, the invention has been accomplished.
The method of adjusting the precipitation rate of the electroless plated film to not more than 2 &mgr;m/hour is not particularly restricted. For example, there are a method of adjusting the temperature of the plating solution to not higher than 50° C., a method of using a tartrate as a complex agent for the plating, and the like. The invention will be described in detail below.
The invention lies in a multilayer printed wiring board comprising a substrate provided with inner conductor circuits, an interlaminar resin insulating layer formed thereon and outer conductor circuits and viaholes formed in the interlaminar resin insulating layer, characterized in that a roughened surface is formed on the surface of the interlaminar resin insulating layer, the outer conductor circuit is comprised of an electroless plated film formed following to the roughened surface and an electrolytic plated film formed on the electroless plated film and the viahole has an average diameter of not more than 90 &mgr;m, and a thickness of the electroless plated film at the bottom of theviahole is 50~100% of a thickness of the electroless plated film at the surface of the interlaminar resin insulating layer.
Further, the invention lies in a method of producing a multilayer printed wiring board, which comprises forming an interlaminar resin insulating layer on a substrate provided with inner conductor circuits, forming an opening having an average diameter of not more than 90 &mgr;m in the interlaminar resin insulating layer, roughening the surface of the interlaminar resin insulating layer, subjecting to an electroless plating to form an electroless plated film so as to follow to the roughened surface on the surface of the interlaminar resin insulating layer, and at the same time subjecting the inside of the opening to an electroless plating to adjust a thickness of the electroless plated film at the bottom of aviahole to 50~100% of a thickness of the electroless plated film on the surface of the interlaminar resin insulating layer, forming a plating resist, subjecting portions not forming the plating resist to an electrolytic plating, removing the plating resist, and removing the electroless plated film beneath the plating resist through etching to form an outer conductor circuit and viaholes comprised of the electroless plated film and the electrolytic plated film.
REFERENCES:
patent: 5571365 (1996-11-01), Maehata et al.
patent: 5827604 (1998-10-01), Uno et al.
patent: 6217987 (2001-04-01), Ono et al.
patent: 6440542 (2002-08-01), Kariya
patent: 6441314 (2002-08-01), Rokugawa et al.
patent: 6541301 (2003-04-01), Raymond
patent: 61163691 (1986-07-01), None
patent: 6-177511 (1994-06-01), None
patent: 9-223859 (1997-08-01), None
patent: 9-246730 (1997-09-01), None
patent: 9-246732 (1997-09-01), None
patent: 10261869 (1998-09-01), None
patent: 11-68308 (1999-03-01), None
English Language Abstract of JP 11-68308.
English Language Abstract of JP 61-163691.
English Language Abstract of JP 6-177511.
English Language Abstract of JP 9-246732.
English Language Abstract of JP 10-261869.
English Language Abstract of JP 9-246730.
English Language Abstract of JP 9-223859.
Asai Motoo
Kariya Takashi
Noda Kouta
Greenblum & Bernstein P.L.C.
Ibiden Co. Ltd.
Nguyen Danny
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