Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1999-01-26
2001-01-16
Gaffin, Jeffrey (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S780000, C361S783000, C361S765000, C174S260000, C174S261000, C228S180210
Reexamination Certificate
active
06175506
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multilayer printed circuit board including a power-supply layer where a plurality of power-supply planes are provided, and more particularly, to a multilayer printed circuit board in which generation of radiation noise is suppressed.
2. Description of the Related Art
Conventionally, when designing a multilayer printed circuit board, it is common to provide at least one power-supply layer and at least one ground layer, in addition to a signal layer. Particularly, in an electronic apparatus operating with conventional digital logic circuits, since the power-supply voltage used in a power-supply layer is mainly 5 V, the entire surface of the power-supply layer is, in most cases, constituted by a 5V single 5V-power-supply plane. Recently, however, as digital ICs (integrated circuits) tend to be operated at a lower voltage and to consume lower power, ICs operated with a 5V power supply and ICs operated with a power-supply voltage of 3.3 V or less have come to be mounted, mixed with each other on a single printed circuit board.
As for substrates incorporated in a computer, in order to reduce power consumption by providing a power management function, 5V and 3.3V power supplies are further divided, for example, into 5V-A, 5V-B and 5V-C, and 3.3V-A, 3.3V-B and 3.3V-C, . . . power supplies, respectively, so that many power supplies are often mixed.
As a result, the power-supply layer of a multilayer printed circuit board is not just a single 5V power-supply plane as in the conventional approach, but is divided into 5V and 3.3V power-supply planes, or still more power-supply planes, in order to supply ICs with different required voltages.
A conventional multilayer printed circuit board will now be described with reference to
FIGS. 11 through 14
.
FIG. 11
is a plan view illustrating the configuration of a first conductive layer in this conventional multilayer printed circuit board.
The first conductive layer comprises a first signal layer
101
provided at the surface side of the multilayer printed circuit board. A first output-side IC
102
operating with a 5V power supply and a second output-side IC
103
operating with a 3.3V power supply are mounted on the first signal layer
101
as electronic devices mounted on the multilayer printed circuit board.
One of the terminals of the first output-side IC
102
is connected to one end of a circuit pattern
104
a
for a 5V clock signal, where a clock signal having an amplitude of 5 V is transmitted. Another end of the circuit pattern
104
a
for the 5V clock signal is connected to a through-hole
105
subjected to interlayer connection to one end of a circuit pattern
104
b
for the 5V clock signal provided on a second signal layer
116
(see FIG.
14
). Another terminal of the first output-side IC
102
is connected to a through-hole
106
subjected to interlayer connection to a power supply layer
112
(see
FIG. 13
) in order to supply the first output-side IC
102
with a power-supply voltage of 5V.
One of the terminals of the second output-side IC
103
is connected to one end of a circuit pattern
107
for a 3.3V clock signal where a clock signal having an amplitude of 3.3 V is transmitted. Another end of the circuit pattern
107
for the 3.3V clock signal is connected to a through-hole
108
connected to an input terminal of a second input-side IC mounted on the second signal layer
116
(see FIG.
14
). Another terminal of the second output-side IC
103
is connected to a through-hole
109
subjected to interlayer connection to the power-supply layer
112
in order to supply the second output-side IC
103
with a suitable power-supply voltage.
FIG. 12
is a plan view illustrating the configuration of a second conductive layer in the conventional multilayer printed circuit board.
The second conductive layer comprises a ground layer
110
provided in an inner layer below the first signal layer
101
. The ground layer
110
is provided in the form of a uniform plane.
FIG. 13
is a plan view illustrating the configuration of a third conductive layer in the conventional multilayer printed circuit board.
The third conductive layer comprises the power-supply layer
112
provided in an inner layer below the ground layer
110
. A 5V-power-supply plane
113
and a 3.3V-power-supply plane
114
are provided on the power-supply layer
112
. The above-described through hole
106
is connected to the 3.3V-power-supply plane
114
.
FIG. 14
is a plan view illustrating the configuration of a fourth conductive layer in the conventional multilayer printed circuit board.
The fourth conductive layer comprises the second signal layer
116
provided at the back of the multilayer printed circuit board. A first input-side IC
117
operating with a 5V power supply and a second input-side IC
118
operating with a 3.3V power supply are mounted on the second signal layer
116
as electronic devices mounted on the multilayer printed circuit board.
One of the terminals of the first input-side IC
117
is connected to one end of the circuit pattern
104
b
for the 5V clock signal, where the clock signal having the amplitude of 5 V is transmitted. Another end of the circuit pattern
104
b
for the 5V clock signal is connected to the above-described through-hole
105
. Another terminal of the first input-side IC
117
is connected to a through-hole
119
subjected to interlayer connection to the power-supply layer
112
in order to supply the first input-side IC
117
with a power-supply voltage of 5 V.
One of the terminals of the second input-side IC
118
is connected to the above-described through-hole
108
. Another terminal of the second input-side IC
118
is connected to a through-hole
120
subjected to interlayer connection to the power-supply layer
112
in order to supply the second input-side IC
118
with a power-supply voltage.
In the above-described conventional multilayer printed circuit board, circuit patterns for various signals (not shown) including the circuit patterns
104
a
,
104
b
and
107
for respective clock signals are provided on the first signal layer
101
and the second signal layer
116
. The circuit patterns
104
a
and
104
b
for the 5V clock signal are connected to each other between the first signal layer
101
and the second signal layer
116
.
Thus, a microstrip structure is provided between the circuit pattern
107
for the 3.3V clock signal provided on the first signal layer
101
, and the ground layer
110
, and a microstrip structure is also provided between the circuit pattern
104
b
for the 5V clock signal provided on the second signal layer
116
, and the power supply layer
112
in a state in which the circuit pattern
104
b
for the 5V clock signal crosses over the 3.3V-power-supply plane
114
.
In the configuration where the ground layer
110
is provided immediately below the circuit pattern
107
for the 3.3V clock signal on the first signal layer
101
, capacitive coupling and inductive coupling between the circuit pattern
107
for the 3.3V clock signal and the ground layer
110
are large. Accordingly, when a signal current flows from the second output-side IC
103
to the second input-side IC
118
via the circuit pattern
107
for the 3.3V clock signal and the through-hole
108
, a return current caused by the signal current rectilinearly flows through a current path
111
on the ground layer
110
immediately below the circuit pattern
107
for the 3.3V clock signal.
In the configuration that the power-supply layer
112
is provided immediately below the circuit pattern
104
b
for the 5V clock signal on the second signal line
116
, capacitive coupling and inductive coupling between the circuit pattern
104
b
for the 5V clock signal and the power-supply layer
112
are large. Accordingly, when a signal current flows from the first output-side IC
102
to the first input-side IC
117
via the through-hole
105
and the circuit pattern
104
b
for the 5V clock signal, a return current caused by the signal current fl
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Foster David
Gaffin Jeffrey
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