Multilayer polysilicon gate self-align process for VLSI CMOS dev

Details Multilayer polysilicon gate self-align process for VLSI CMOS dev Multilayer polysilicon gate self-align process for VLSI CMOS dev

1993-05-03

1994-09-27

Padgett, Marianne

Fishing, trapping, and vermin destroying

437 28, 437 41, 437 43, 427526, 427427, 427255, 4272553, H01L 21265, B05D 306, C23C 1600

Patent

active

053506987

ABSTRACT:
A new method of forming a self-aligning polysilicon gate is described. A gate silicon oxide is formed over a silicon substrate. A polysilicon layer is formed over the gate oxide. A native silicon oxide layer is formed over the polysilicon layer. A second polysilicon layer is formed over the native silicon oxide layer. Additional alternating layers of polysilicon and native silicon oxide are formed as desired. The wafer is annealed at between about 800.degree. to 1000.degree. C. This causes, it is believed, the silicon oxide gas from the multiple native silicon oxide layers to be exhausted resulting in the removal of all silicon oxide layers. A polycide layer is formed overlying the multiple polysilicon layers, if desired. Conventional lithography and etching techniques are used to form a gate. Ions are implanted into the substrate to form source/drain regions, using the multilayer gate as a mask. Rapid thermal annealing activates the impurities. A dielectric layer is deposited followed by conventional metallization techniques to complete construction of the integrated circuit.

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