Multilayer overlay interconnect for high-density packaging of ci

Details Multilayer overlay interconnect for high-density packaging of ci Multilayer overlay interconnect for high-density packaging of ci

1992-06-05

1993-08-17

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With large area flexible electrodes in press contact with...

257690, 257719, 257727, 257773, 257759, 257785, H01L 2316

Patent

active

052372030

ABSTRACT:
A multilayer overlay interconnect for packaging various circuit elements such as integrated-circuit (IC) chips in high-density configurations. The overlay interconnect allows multiple IC chips to be removably mounted and electrically interconnected within a chip package with minimized interconnection lengths between the IC chips, for improved high speed operation of the chips. In addition, the back side of the chips remain accessible for making direct contact with a heat sink and/or a substrate interconnect which provides for good heat dissipation and/or additional electrical contact areas. The multilayer overlay interconnect is either flexible or both flexible and compressible. The overlay interconnect includes a plurality of thin polymer layers, a plurality of inner contact areas on an outermost layer for making electrical contact with contact areas on the IC chips, a plurality of outer contact areas on the outermost layer for making electrical contact with contact areas on leads extending into the chip package, and electrically-conductive traces on one or more of the layers, with interconnecting vias, for interconnecting the inner and outer contact areas. The overlay interconnect further includes cut-out regions to accommodate for substantial variations in circuit element thicknesses or circuit elements which require a medium of air to operate properly.

REFERENCES:
patent: 4721995 (1988-01-01), Tanizawa
patent: 5029325 (1991-07-01), Higgins et al.

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