Multilayer metallization method for integrated circuits

Details Multilayer metallization method for integrated circuits Multilayer metallization method for integrated circuits

1987-06-22

1989-04-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437189, 437195, 437194, 437196, 357 67, 357 71, H01L 2348

Patent

active

048248037

ABSTRACT:
Metal contacts and interconnections for semiconductor integrated circuits are fabricated through the deposition of a sandwich structure of metal. The bottom layer of a refractory metal prevents aluminum spiking into silicon; the top layer of refractory metal or alloy serves to reduce hillocking of the middle layer of conductive material. The upper layer of refractory metal at the location of the contact pads is etched off to improve bonding during packaging.

REFERENCES:
patent: 4507852 (1985-04-01), Karulkar
patent: 4527184 (1985-07-01), Fischer
patent: 4556897 (1985-12-01), Yorikane et al.
patent: 4650543 (1987-03-01), Kishita et al.
Ghandhi, Sorab K., VLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 492-497.
Chow, T. P. and A. J. Steckl, "Plasma Etching of Refractory Gates for VLSI Applications", J. Electrochemical Society: Solid-State Science and Technology, Oct. 84, pp. 2325-2335.
Ghandhi, Sorab K., VLSI Fabrication Principles, John Wiley & Sons, New York, 1983, pp. 502-510.

Affiliated with

Also associated with

Rating

Multilayer metallization method for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilayer metallization method for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayer metallization method for integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1195718