Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
1999-02-22
2002-04-30
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S040000, C257S725000
Reexamination Certificate
active
06380553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention concerns a multilayer matrix-addressable logic device or processor device with two or more individually matrix-addressable stacked thin films of an active material which under the influence of an electric current or an electric field can attain two or more physically or chemically distinct detectable stable or metastable states wherein each are assigned respective logical values and which can transfer from a state of this kind to another, wherein the active material in each layer is provided between a first electrode set and a second electrode set which each comprises substantially mutually parallel striplike electrodes, such that the electrodes in the first electrode set constitute the columns and the electrodes in the second electrode set the rows in a substantially orthogonal array, wherein the intersections between the electrodes in the array defined logic cells in the layer of active material and wherein the stacked layers of active material is provided on a common supporting substrate.
2. Description of Related Art
From Norwegian patent application No. 972 803 filed on Jun. 17, 1997 which is assigned to the present applicant and hereby incorporated by reference, there is as shown in
FIG. 1
known an electrically addressable passive device realized as a matrix-addressable device. A functional medium
1
is provided in the form of a plane layer S. The functional medium is an organic material with non-linear impedance characteristic and possible with different substances added in order to realize the desired detecting or switching functions. On the upper surface of the layer S lines for electrical addressing are provided in the form of a plurality of parallel electrical conductors m and on the lower surface of the layer S lines are correspondingly provided in the form of parallel electrical conductors n for electrical addressing, the conductors m,n being provided mutually orthogonal such that they form an array. In
FIG. 1
the device is shown with x conductors m and y conductors n such that the conductors form an orthogonal x,y array. A logic cell
2
in the device is generated in the volume between two intersecting electric conductors m,n. This is emphasized in
FIG. 1
by the formation of a logic cell
2
k1
in the intersection between the k′th conductor m and the
1
′th conductor n.
FIG. 2
shows a section through a logic cell
2
k1
of this kind according to the prior art. The opposite portions of the conductors m
k
and n
1
in an intersection together realize the electrode means E
k1
of the logic cell
2
k1
, as the anode
3
of the electrode means may be the conductor m
k
and the cathode
4
of the electrode means the conductor n
1
.
For the purposes of the present invention the logic cell
2
k1
could be denoted as a logic element, as the material in the functional medium
1
in the cell
2
k1
on addressing can attain different physical and chemical states which may represent electrically detectable logical values. As further shown in
FIG. 2
, the functional medium
1
is provided as a portion of the layer S between the electrodes m
k
, n
1
, the anodes
3
and the cathodes
4
of the electrode device E
k1
being realized by the respective relevant portions of the conductor m
k
and the conductor n
1
in the intersection between the conductors. In this intersection, i.e. between the anode
3
and the cathode
4
, a passive logic cell
2
k1
is formed and denoted in this manner to indicate that it is provided between the conductor m
k
and the conductor n
1
.
FIG. 2
is, of course, only a section of FIG.
1
and it is to be understood that the whole section taken along the conductor m
k
will show a total of y logic cells
2
and y conductors n
1
. If x≠y, the device, of course, forms a rectangular area with x,y logic cells and if x=y, the device is square with x
2
cells.
As shown in
FIG. 1
, the known device realizes a passive matrix, i.e. it can be addressed without using switching components in each cell or in each intersection, but for the purpose of the present application the matrix may also be of the active type, i.e. a switching element is including in each intersection and in each cell in the matrix. Active matrices of this kind which for instance employ transistors, are well-known in the art.
Applied as a memory medium, i.e. for storage of data, the functional medium
1
, as shown in
FIGS. 1 and 2
according to prior art, responds to electrical stimuli which effect a reversible or an irreversible change in the physical or chemical properties, which represents a given logical state, for instance a binary 1 or 0, and which can be detected by suitable means as the complex impedance between the electrodes or as the transmitting or reflecting optical properties of the memory medium or functional medium. Examples of reversible memory mediums which can be used in erasable and rewriteable memories are liquid crystals, metal-organic compounds, doped polymers and ferroelectric materials. Examples of irreversible memory materials which can be used in read only memories (ROM), or memories of the WORM type (Write Once Read Many Times) are polymers which are doped in order to obtain a controllable electrical rectification and conductance.
As shown in
FIG. 1
or FIG.
2
and according to prior art the functional medium
1
may comprise one or more layers of active materials provided in a sandwich between the electrodes. Physically structures of this kind are realized on a substrate which may be rigid or flexible. Increased capacity may be obtained in a more compact embodiment, for instance by using thin substrates in the form of plastic films or strips and stacking these upon each other. However, the highest stacking density which is obtainable in this manner is restricted by a number of factors, among them the minimum practical substrate thickness. For the most relevant materials this will lie in a range of 1-10 &mgr;m.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention hence is to be able to stack an array modules of the kind shown in
FIG. 1
on a common substrate and sequentially provide a plurality of such array modules stacked one above the other, such that a stacked array configuration is obtained with an optimal given form factor which, apart from scale, is not changed by the number of stacked layers or array modules.
Further it is an object of the invention that the stacked array configuration may be given desired electrical, mechanical or thermal properties with regard to optimal functionality independent of the addressing mode.
According to the present invention the above objects and advantages are realized with a multilayer matrix-addressable logic device with two or more individually matrix-addressable stacked thin film of an active material, characterized in that a separation layer is provided between each layer of active material. Advantageously, the separation layer according to the invention is either electrically conducting or has high thermal conductivity.
Advantageously, the separation layer according to the invention may comprise a planarization material, the planarization material being provided in a separate planar layer integrated with the separation layer itself. The separation layer according to the invention may advantageously also be realised as a mechanical, thermal or thermo-mechanical oscillation damper.
Finally, the separation layer according to the invention may advantageously consist of respectively a metal, a metal alloy, a semiconductor, a carbonaceous material, diamond-like carbon or a nanocomposite.
The invention shall now be discussed in more detail with reference to the accompanying drawing wherein
REFERENCES:
patent: 4939568 (1990-07-01), Kato et al.
patent: 5612570 (1997-03-01), Eide et al.
patent: 5637912 (1997-06-01), Cockerill et al.
patent: 5675180 (1997-10-01), Pedersen et al.
Article from the Norwegian Newspaper “Aftenposten” of Jun. 22, 1997 “Superkortet” (with English language translation thereof “The Sup
Gudesen Hans Gude
Nordal Per-Erik
Lackenbach Siegel
Ngo Ngan V.
Nissen J. Harold
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