Multilayer laser trim interconnect method

Details Multilayer laser trim interconnect method Multilayer laser trim interconnect method

2002-07-17

2004-06-29

Vu, Hung (Department: 2811)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S108000, C438S111000, C438S123000, C438S613000, C438S617000

Reexamination Certificate

active

06756252

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for semiconductor packaging and assembly, and in particular to a method for creating improved interconnections between a die and package substrate. Still more particularly, the invention relates to a method for creating interconnects with subsequent layers of insulating and conductive materials.
2. Background Information
Modern-day semiconductor devices, commonly called microchips, or “die,” are fabricated on wafers, and the wafers are then sawn into grids, separating the individual chips prior to assembly in a package. Chips are fabricated in a variety of sizes, but typically range from only a few millimeters to a couple of centimeters or more in width. Each chip has numerous electrical signals. Processors, for example, may have several hundred signals. Provisions must be made to electrically connect a die to the component with which it is used (typically, other electrical devices and connections on a printed circuit board) and also to protect the die from damage or other external conditions that could hinder its operation. Package engineering, or packaging, is the field within semiconductor engineering that addresses these needs.
Typically, as a die is designed, a packaging team will assess its layout and other requirements to determine the ideal packaging solution. A myriad of requirements may exist for a particular device, including thermal, reliability, moisture, electrical, package size and cost requirements. As semiconductor devices increase in complexity and shrink in size, packaging them is becoming more and more challenging as a greater numbers of electrical signals and other connections, such as grounds, have to be routed from increasingly smaller chips. As this “pin count” increases, new methods must be found to electrically connect the die to the board while continuing to meet increasingly aggressive packaging needs.
Referring now to
FIG. 1
, signals are typically routed from a die
10
by a ring of substantially square electrical “bond pads”
12
located on the edge of the die surface
14
. These miniscule bond pads
12
may be less than five one-hundredths of a millimeter (0.05 mm) wide, and spaced just slightly farther apart, to account for surrounding circuitry
16
.
Historically, as shown in
FIG. 2
, chips with a relatively low “pin count,” or number of bond pads, have been packaged using “leadframes”
20
, thin etched or stamped metal frames which have a central area, or flag
22
, to which a chip is attached. Referring now to
FIG. 3
, leadframes
20
generally have metal “fingers”
30
, pointing inward towards flag
22
, which are connected to substantially square electrical “bond pads”
12
around the edge of die
10
with hair-like wires
32
, which may be 25 thousandths of a millimeter (0.025 mm) or smaller in diameter. This assembly process, called “wirebonding,” is performed by extremely precise robotic machines called wirebonders (not shown).
FIG. 4
shows a full die
10
wirebonded to a leadframe
20
.
As shown in
FIG. 5
, once the die
10
has been attached to flag
22
by an epoxy
50
or other adhesive and bonded to leadfingers
30
with wires
32
, the die
10
is then encapsulated, typically with a solid plastic mold compound
52
, or ceramic housing (not shown). Lead fingers
30
then carry the signals out of the edges of the package
54
by doubling as “feet”
56
that are fashioned to contact or pass through specific electrical “lands” (not shown) on the board
58
.
Several issues exist with peripherally leaded packages. For instance, as all the signals on the die must be routed out the edge of the package, as pin count increases, the footprint of the package may be undesirably forced to increase geometrically since the package area is not utilized for interconnects. Current leaded packages are typically offered in certain predetermined pin counts (such as 100, 112, or 144 leads) with each pin count corresponding to a certain size package (e.g., 10×10, 14×14 or 20×20 mm). For this reason, small increases in the pin count of the die can cause relatively large increases in overall package area, since exceeding the number of pins in one package size would force the die into the next larger package family.
The desire to reduce the size of consumer and other types of electronics (e.g., cell phones, laptop computers, etc.) creates pressure on chip manufacturers to reduce the size of semiconductor packages. Further, a myriad of issues exists with wirebonding, the default interconnect method used with leadframe packages. Referring now to
FIG. 6
, in the case of plastic packaging, a solid mold compound (not shown) is often unidirectionally injected into the corner of a mold cavity (not shown) around the wirebonded die
10
and spreads out in a pattern
60
. The solid mold compound serves to protect the chip and interconnects.
As the mold compound spreads over die
10
, it contacts and pushes against wires
32
causing them to bend out or “sweep” a small distance as shown. For this reason, packaging design guidelines limit wire length and pitch, or the distance between adjacent wires
32
, to prevent shorting. For a fine-pitch die, or a die that requires a wire pitch smaller than current high-volume industry standards, and thus, requires a special wirebonder and thinner wires
32
, the issue of wire sweep becomes even more troublesome.
Wire sag is also an issue with relatively long or thin wires, which have an inherent sag under their own weight due to their extremely small cross-sections. It is essential that wires do not contact the edges of the die or lead fingers to prevent physical damage. A satisfactory wirebond
32
is shown in
FIG. 7A
, whereas
FIG. 7B
shows a drooping wire
32
coming into close contact with the edges of both the die
10
at
72
and lead fingers
30
at
74
.
Wirebonding also adds unwanted height to a package
54
, since a wirebonding tool (not shown) will typically create a bond by forming a small ball of metal
70
on a bond pad
12
on the edge of die
10
, then arc a wire
32
up from ball
70
, finally stitching it out to a finger
30
on leadframe
20
. For small products, such as cell phones or other popular mobile devices, any added semiconductor package height is undesired.
For these reasons, die with high pin counts or die used in small electronics typically utilize area array packages, one of the most common being the ball grid array (BGA)
80
, as shown in
FIG. 8A
, in which an array of solder balls
82
covers at least part of the bottom surface of a thin, multi-layered board, or substrate
84
.
As shown in
FIG. 8B
, when assembled in a BGA package
80
, the die
10
is bonded to the central flag
86
of substrate
84
, rather than a metal leadframe. Instead of routing signals from the package periphery down to the board
58
as with a leadframe package, in an area array package, a die
10
may be wirebonded out to conductive “traces”
88
on the substrate
84
. These individual traces
88
can pass down through the substrate layers using electrically conductive channels, or vias
89
, and down to the bottom layer of the substrate
84
, where they are routed to an array of solder balls
82
, which serve as interconnects to a matching array on the board
58
.
Packaging using substrates
84
affords considerable routing flexibility, as space may be conserved by overlapping different signal traces
88
on different layers of the substrate
84
. Further, sensitive signals, which would otherwise interfere with one another if routed out adjacently, may be isolated from one another by surrounding them on the substrate bottom with surplus balls
82
.
While area array packaging has met many packaging challenges, the practice of wirebonding still limits the capabilities and features of a packaged device. More advanced methods of attaching a die to a substr

Affiliated with

Also associated with

Rating

Multilayer laser trim interconnect method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilayer laser trim interconnect method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayer laser trim interconnect method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3298340