Multilayer interconnection technique

Details Multilayer interconnection technique Multilayer interconnection technique

1996-11-19

1999-04-27

Goodrow, John

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

438129, H01L 2182

Patent

active

058973427

ABSTRACT:
A multilayer wiring structure consists of a substrate with a first set of wiring lines formed thereon. A first insulating layer covers the first set of wiring lines, a second insulating layer covers the first set of wiring lines and then a second set of wiring lines are formed on the second insulating layer. Vias are formed through the second insulating layer, the second wiring lines and the first insulating layer extending down to the surface or near the surface of the first wiring lines. Metallizations fill the vias to form connections and interconnections to and between the first wiring lines, the second wiring lines and the surface of the semiconductor device. Additional wiring lines may be formed on the surface of the second insulating layer and in contact with the metallizations.

REFERENCES:
patent: 4582563 (1986-04-01), Hazuki et al.
patent: 5204286 (1993-04-01), Doan
patent: 5279988 (1994-01-01), Saadat et al.
patent: 5493152 (1996-02-01), Chang
patent: 5610100 (1997-03-01), Kurino et al.

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