Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2000-07-20
2004-01-13
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
Reexamination Certificate
active
06677682
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a multilayer interconnection technique.
2. Description of the Background Art
In recent years, a wiring has become finer and more multilayered with an enhancement in the integration and function of a semiconductor device. In a method of manufacturing the semiconductor device, a multilayer interconnection technique has been one of important techniques.
FIG. 17
is a longitudinal sectional view illustrating a conventional semiconductor device
101
P having a two-layer interconnection structure. The semiconductor device
101
P comprises a silicon substrate
1
P. In
FIG. 17
, various elements formed on a surface of the silicon substrate
1
P are omitted.
An interlayer insulating film
2
P composed of a silicon oxide (SiO
2
) is formed on the silicon substrate
1
P. The interlayer insulating film
2
P is provided with a contact hole
2
HP in a direction of a thickness thereof and a hole
2
MP for a mark such as an alignment mark. In a semiconductor device having a minimum line width of 0.25 &mgr;m, that is, a so-called quarter micron generation semiconductor device, generally, in the case in which the semiconductor device
101
P is seen from an upper surface, the contact hole
2
HP and a via hole
4
HP which will be described below have dimensions of approximately 0.3 to 0.4 &mgr;m and the hole
2
MP for a mark has a dimension of approximately 1 to 10 &mgr;m.
A metal layer
7
HP forming a so-called plug is buried in the contact hole
2
HP. The “plug” means a conductive layer for electrically connecting conductive layers such as wirings provided with an interlayer insulating film interposed therebetween. On the other hand, a metal layer
7
MP having the shape of a so-called side-wall spacer is formed on a side wall of the hole
2
MP for a mark. The metal layer
7
MP is formed of the same material as the material of the metal layer
7
HP.
Furthermore, a metal layer
3
HP constituting a wiring or a wiring layer is formed on the interlayer insulating film
2
P in contact with the plug
7
HP. On the other hand, a metal layer
3
MP is formed to cover the hole
2
MP for a mark.
An interlayer insulating film
4
P composed of a silicon oxide is formed to cover the wiring
3
HP, the metal layer
3
MP and the interlayer insulating film
2
P. The interlayer insulating film
4
P has a thickness of approximately 700 to 1000 nm (7000 to 10000 angstrom), for example. The interlayer insulating film
4
P has a contact hole or a via hole
4
HP reaching the wiring
3
HP and the via hole
4
HP is filled with a plug
8
HP. A wiring
6
HP is formed on the interlayer insulating film
4
P in contact with the plug
8
HP. On the other hand, a concave portion
4
MP is formed above the hole
2
MP for a mark on the surface
4
SP side of the interlayer insulating film
4
P which is opposite to the substrate
1
.
In
FIG. 17
, a region HP including the plugs
7
HP and
8
HP, the wirings
3
HP and
6
HP and the like is equivalent to an element region or an element formation region where various elements (not shown) of the semiconductor device
101
P are formed. On the contrary, a region MP including the hole
2
MP for a mark is equivalent to a region where an auxiliary pattern such as an alignment mark to be used in a manufacturing process is formed.
Next, a method of manufacturing the conventional semiconductor device
101
P will be described below with reference to each of longitudinal sectional views of
FIGS. 18
to
20
in addition to FIG.
17
.
First of all, a silicon oxide (plasma oxide) is deposited, by a plasma CVD (Chemical Vapor Deposition) method, on a silicon substrate
1
P where the above-mentioned various elements are formed. The silicon oxide is flattened by using an etch-back method or a CMP (Chemical Mechanical Polishing) method, thereby forming an interlayer insulating film
2
P.
Next, the interlayer insulating film
2
P is wholly coated with a resist (not shown). The resist is patterned to have such a pattern as to correspond to a contact hole
2
HP, a hole
2
MP for a mark and the like by a photolithographic technique. By a RIE (Reactive Ion Etching) method using the patterned resist as a mask, the interlayer insulating film
2
P is opened to form the contact hole
2
HP and the hole
2
MP for a mark. Then, the resist is removed by an oxygen plasma or the like.
Subsequently, a predetermined metal material is deposited by a sputtering method, for example, to cover the whole interlayer insulating film
2
P. Then, the metal layer is etched back to form a plug
7
HP. At this time, the dimension of the hole
2
MP for a mark is greater than that of the contact hole
7
HP as described above. In the hole
2
MP for a mark, therefore, the metal layer remains in the form of a side-wall spacer, thereby constituting a metal layer
7
MP.
Then, a predetermined metal material is deposited to cover the whole interlayer insulating film
2
HP. Thereafter, the whole metal layer is coated with a resist (not shown). The resist is patterned to have such a pattern as to correspond to a wiring
3
HP and a metal layer
3
MP by a photolithographic technique. Then, the metal layer is patterned to form the wring
3
HP and the metal layer
3
MP by a RIE method using the patterned resist as a mask. Subsequently, the resist is removed by the oxygen plasma or the like. By the above-mentioned steps, a semiconductor device in the state shown in
FIG. 18
is obtained.
As shown in
FIG. 19
, then, a silicon oxide film
4
AP having a thickness of approximately 1500 to 2500 nm (15000 to 25000 angstrom), for example, is formed by using a plasma CVD method to wholly cover the interlayer insulating film
2
P, the wiring
3
HP and the metal layer
3
MP.
The silicon oxide film
4
AP is formed to have a concave portion
4
MAP corresponding to the concave shape of the hole
2
MP for a mark above the hole
2
MP for a mark. Such a concave portion
4
MAP is easily formed above the comparatively large hole
2
MP for a mark as in the case in which the hole
2
MP for a mark in a plane view of the silicon substrate
1
P has a dimension of approximately 1 &mgr;m or more, for example. Moreover, in the case in which the hole
2
MP for a mark has such a depth as to exceed 1.5 &mgr;m, for example, the concave portion is easily formed deeply.
Next, the silicon oxide film
4
AP is polished and flattened by using the CMP method to form an interlayer insulating film
4
P shown in FIG.
20
. In this case, the silicon oxide film provided on the wiring
3
HP is polished to have a thickness of approximately 700 to 1000 nm as described above. A bottom part of the concave portion
4
MAP shown in
FIG. 19
remains as the concave portion
4
MP shown in FIG.
20
.
In the case in which the silicon oxide is polished by using the CMP method, a silica (SiO
2
) or ceria (CeO
2
) based slurry is often used. In respect of productivity, the ceria based slurry having a higher polishing rate is often selected.
Then, a via hole
4
HP, a plug
8
HP and a wiring
6
HP are formed by the same forming method as the method of forming the contact hole
2
HP and the like described above. By the above-mentioned steps, the semiconductor device
101
P shown in
FIG. 17
is obtained. In the case of a multilayer wiring having three layers or more, the above-mentioned steps are repeated predetermined times.
Thereafter, an interlayer insulating film is formed to cover an uppermost wiring, and a silicon nitride film to be a passivation film is formed over the whole surface of the interlayer insulating film by the plasma CVD method or the like. Subsequently, the interlayer insulating film and the like provided on a bonding pad (not shown) are removed by using a photolithographic technique and a dry etching method, thereby exposing the bonding pad.
In the case in which the silicon oxide is polished by using the CMP method as described above, the ceria based slurry having a high polishing rate is often us
Fujiki Noriaki
Harada Shigeru
Yamashita Takashi
Loke Steven
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Owens Douglas W.
Renesas Technology Corp.
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