Patent
1977-01-03
1978-10-17
James, Andrew J.
357 65, 357 67, 357 68, H01L 2348, H01L 2946, H01L 2954
Patent
active
041212410
ABSTRACT:
A semiconductor integrated circuit structure wherein a first metal interconnecting system is formed on a semiconductor body having active and/or passive elements formed therein. An insulating layer is deposited on the first metal interconnecting system. Apertures are formed in selected regions of such layer and are cleaned in a sealed sputtering chamber. A refractory metal is deposited over the insulating layer and through the apertures onto the first metal interconnecting system in a sealed sputtering chamber. A lead metal is deposited over the refractory metal layer. Selected portions of such refractory metal and lead metal are removed to form a second metal interconnecting system. With such structure and method the surfaces of the first metal interconnecting system which are to be connected to a second metal interconnecting system through the apertures are cleaned of oxides and other contaminates in a sealed sputtering chamber and are then sealed from further contamination by the refractory metal layer. The structure and method improves the electromigration resistance of the second metal interconnecting system because of the presence of the refractory metal layer. Further, the refractory metal layer acts as a barrier layer which prohibits interdiffusion between the connected portions of the first and second interconnecting systems. The assurance of good ohmic contact between the connected portions of the interconnecting systems reduces the surface area required for metalization.
REFERENCES:
patent: 3754168 (1973-08-01), Cunningham
patent: 3801880 (1974-04-01), Harada et al.
patent: 3833842 (1974-09-01), Cunningham
patent: 3879840 (1975-04-01), Ames
patent: 4023197 (1977-05-01), Magdo et al.
Drake Jerry W.
Portesi Peter J.
James Andrew J.
Pannone Joseph D.
Raytheon Company
Sharkansky Richard M.
LandOfFree
Multilayer interconnected structure for semiconductor integrated does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multilayer interconnected structure for semiconductor integrated, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayer interconnected structure for semiconductor integrated will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-379502