Multilayer interconnect structure for semiconductor device and m

Details Multilayer interconnect structure for semiconductor device and m Multilayer interconnect structure for semiconductor device and m

1997-02-12

1998-02-17

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257758, 257763, 257764, 257765, 257774, 257915, H01L 2941

Patent

active

057194467

ABSTRACT:
A multilayer interconnect structure for a semiconductor device. The structure comprises a lower patterned metallization layer, a higher patterned metallization layer, and filled holes for electrically interconnecting these two layers. The two metallization layers are formed out of aluminum or an aluminum alloy by high-temperature aluminum sputtering or aluminum reflow techniques. A suction-preventing layer is formed either at the bottoms of the contact holes or on the surface of the lower metallization layer to prevent the material of the lower metallization layer from being sucked into the overlying contact holes.

REFERENCES:
patent: 4816424 (1989-03-01), Watanabe et al.
patent: 4937652 (1990-06-01), Okumura et al.
patent: 4987562 (1991-01-01), Watanabe
patent: 5202579 (1993-04-01), Fujii et al.
patent: 5278448 (1994-01-01), Fujii
patent: 5313100 (1994-05-01), Ishii et al.
patent: 5317187 (1994-05-01), Hindman et al.
patent: 5341026 (1994-08-01), Harada et al.
patent: 5356836 (1994-10-01), Chen et al.
patent: 5358901 (1994-10-01), Fiordalice et al.
patent: 5371410 (1994-12-01), Chen et al.
patent: 5374592 (1994-12-01), MacNaughton et al.
patent: 5391517 (1995-02-01), Gelatos et al.
patent: 5488014 (1996-01-01), Harada et al.
patent: 5523259 (1996-06-01), Merchant et al.
patent: 5543357 (1996-08-01), Yamada et al.
patent: 5594278 (1997-01-01), Uchiyama
patent: 5604155 (1997-02-01), Wang

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