Multilayer inductor and method of manufacturing the same

Inductor devices – Windings – Having conductor of particular shape

Reexamination Certificate

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C336S200000, C336S232000

Reexamination Certificate

active

06452473

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to an inductor used for a high frequency circuit such as a mobile communication apparatus and instruments. More particularly, it relates to a laminated or multi-layered inductor having a miniaturized configuration and for a high frequency application and a method of producing such an inductor.
A laminated inductor, which is illustrated at reference numeral
2
in FIGS.
14
(
a
) and
14
(
b
), is known to have a structure of a chip component (of semiconductor integrated circuits) which permits “surface mounting” so that it can be mounted on printed circuit boards, etc. The laminated inductor
1
has terminal electrodes
4
,
5
at opposed ends of the chip for connection with outer circuits, and a coil
3
in the chip so that ends of the coil
3
extend outside to be connected with the outer circuits. The coil
3
is formed such that electrically insulating layers of either magnetic material or non-magnetic material and conductive patterns are alternately superimposed or laminated with each other, and the ends of each of the conductive patterns are connected in turn to form a laminated construction.
Soldering properties of the terminal electrodes
4
,
5
at the time of surface mounting are largely dominant or influential to a reliability of the chip components and, therefore, in order to ascertain a suitable bonding strength, the terminal electrodes
4
,
5
are formed into a box-like structure to enclose the end surfaces of the chip component so that the box-like structure covers the side surfaces and upper and lower surfaces of the chip, as illustrated in FIGS.
14
(
a
) and
14
(
b
).
However, in the box-like structure of the electrodes described above, its end portions are extended inwardly toward the coil
3
in the chip so that the terminal electrodes
4
,
5
are positioned closer to each other. Therefore, it is likely that a stray capacitance C is generated between the terminal electrodes
4
,
5
and the coil portions (that is, the upper-right and lower-left portions of the box-like structure of FIG.
14
(
b
)) where an electric potential is relatively large. Consequently, the resonance frequency is not as increased as expected by the influence of the stray capacitance C, and the Q-factor of the coil is lowered. Thus, there is a problem that it is difficult to provide a suitable application for a high frequency. Particularly, through a recent diffusion and spread of personal computers (PC) and local area network (LAN), a large demand has been made to use an ultra-high frequency band exceeding 2 GHz, and it has been necessary to meet with the requirement of further and higher frequency applications due to an increase of resonance frequency, in the chip type laminated inductor.
In order to lower a stray capacitance, it is sufficient to minimize the extended portions of the terminal electrodes
4
,
5
. In the conventional method of forming the terminal electrodes
4
,
5
, a complex technique, which is called a dip method, has been used to dip a tip end into a predetermined depth of a paste for the terminals, but this method has some difficulties in seeking a high dimensional accuracy due to stain and soil of the paste. Accordingly, it has been extremely difficult to provide small sized electrodes. Furthermore, reduction of the extended portions of the terminal electrodes results in another disadvantage of lowering the bonding strength at the time of the mounting or packaging of parts and elements.
At the time of dipping in the dip method, it is necessary to have a portion in the chip for holding the chip itself. However, in the case of a micro-structured chip such as, for example, Type 0603 (that is, 0.6 mm×0.3 mm×0.3 mm), there is less space in the chip itself for the holding portion and, therefore, the electrode structure as described above has been a bottle neck for meeting the requirement of micro-structure or micro-miniaturization. Thus, the conventional laminated inductor has serious problems with respect to reliability, performance capability and production efficiency in coping with the recent requirement of miniaturization, thinner designing, higher speed operation, etc.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide, in view of the problems and difficulties in the conventional structure, an improvement in a laminated inductor.
Another object of the present invention is to provide a new laminated inductor, which permits reduction of stray capacitance between the coil and the terminal electrodes so that the inductor is adaptable for a high frequency application.
A further object of the present invention is to provide an improved laminated inductor which has a suitable bonding strength at the chip mounting step and which meets the requirements of micro-miniaturization.
Another object of the invention is to provide a method of forming the improved laminated inductor described above.
According to a first aspect of the present invention, there is provided a laminated inductor comprising a plurality of electrically insulating layers (
2
), a plurality of electrically conductive patterns, and terminal electrodes. The electrically insulating layers and the conductive patterns are alternately superimposed with each other, and the electrically conductive patterns are connected with each other at the ends thereof to form a coil (
3
) in a laminated form. The terminal electrodes (
4
,
5
) are arranged at opposed end portions of a chip, and a starting end and a terminal end of the coil extend, to connect the terminal electrodes. The terminal electrodes are formed on at least opposed end surfaces (
1
d
) and a lower surface (
1
b
) of the chip.
According to a modification of the structure of the invention described above, the terminal electrodes are formed not only on the opposed end surface and the lower surface of the chip but also on an upper surface of the chip.
FIG. 3
shows a case in which no terminal electrode is provided on the upper surface and the side surface of the chip, and
FIG. 4
shows a case in which no terminal electrode is provided on the side surface of the chip. In the electrode structure of either case, distance between the coil and the extended portion of the terminal electrode can be reduced relative to the conventional structure. Therefore, a stray capacitance between the coil and the electrode can be reduced so that the structure of the present invention can meet with the requirement of high frequency applications.
In a second aspect of the invention, the terminal electrodes (
4
,
5
) on both the upper and lower surfaces (
1
a,
1
b
) of the chip is formed during a laminating process of production.
By forming the electrodes on the upper and lower surfaces of the chip in the process of the lamination for forming the coil, it is sufficient to apply an electrode paste to the limited surface to which the conductive material is coupled. In other words, the application of the electrode paste can be limited to the connecting portion of the conductive member. Therefore, it is not necessary to prepare expensive equipment for controlling a flow or running the paste extensively to an unnecessary portion which has been needed in the conventional dip method. Thus, the production procedure can be simplified to provide reduction in manufacturing cost.
In a third aspect of the invention, the terminal electrode surface on the upper surface of the chip is made smaller in size than the terminal electrode surface on the lower surface of the chip.
With respect to the size of the terminal electrodes described above, since electrical measurements are generally conducted by contacting a measurement terminal to an upper surface of the chip, a relatively large terminal electrode of the upper surface will be convenient to proceed the contact of the measurement terminal onto the electrode. However, providing a large terminal electrode causes generation of a stray capacitance. In the embodiment of the invention, as shown in
FIG. 5
, the electrode on the upper surf

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