Semiconductor device manufacturing: process – Gettering of substrate – By layers which are coated – contacted – or diffused
Reexamination Certificate
2006-07-03
2010-06-15
Le, Thao X (Department: 2892)
Semiconductor device manufacturing: process
Gettering of substrate
By layers which are coated, contacted, or diffused
C438S310000, C438S471000, C257SE21318, C257SE29108
Reexamination Certificate
active
07737004
ABSTRACT:
In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.
REFERENCES:
patent: 4053335 (1977-10-01), Hu
patent: 4559086 (1985-12-01), Hawkins
patent: 4608096 (1986-08-01), Hill
patent: 4645546 (1987-02-01), Matsushita
patent: 4698900 (1987-10-01), Esquivel
patent: 4892840 (1990-01-01), Esquivel
patent: 5008722 (1991-04-01), Esquivel
patent: 5397903 (1995-03-01), Hirose
patent: 5444001 (1995-08-01), Tokuyama
patent: 5753560 (1998-05-01), Hong
patent: 5757063 (1998-05-01), Tomita
patent: 5784167 (1998-07-01), Ho
patent: 5874325 (1999-02-01), Koike
patent: 5882990 (1999-03-01), DeBusk et al.
patent: 5895236 (1999-04-01), Yaoita
patent: 6146980 (2000-11-01), Hsu
patent: 6277194 (2001-08-01), Thilderkvist et al.
patent: 6376336 (2002-04-01), Buynoski
patent: 6482749 (2002-11-01), Billington et al.
patent: 6531378 (2003-03-01), Hopfner
patent: 6639327 (2003-10-01), Momoi
patent: 6670259 (2003-12-01), Chan
patent: 6890838 (2005-05-01), Henley
patent: 2006/0008997 (2006-01-01), Jang et al.
patent: 2007/0010037 (2007-01-01), Li et al.
patent: 60176241 (1985-09-01), None
Ibok, E., Garg, S., A Characterization of the Effect of Deposition Temperature on Polysilicon Properties, J. Electrochem. Soc., vol. 140, No. 10, Oct. 1993, p. 2933.
Istratov, A., Vainola, H., Huber, W., Weber, E., Gettering in silicon-on-insulator wafers: experimental studies and modelling, Semiconductor Science Technology 20 (2005) 568-575.
Kamins, T. I., Manoliu, J., Tucker, R. N., Diffusion of Impurities in Polycrystalline Silicon, J. Appl. Phys., vol. 43, No. 1, Jan. 1972.
Meakin, D., Stoemenos, J., Migliorato, P., Economou, N. A., Structural studies of low-temperature low-pressure chemical deposited polycrystalline silicon, J. Appl. Phys., vol. 61(11), Jun. 1987.
Lorenc Michal
Lysacek David
Valek Lukas
Jackson Kevin B.
Jones Eric W
Le Thao X
Semiconductor Components Industries LLC
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