Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-10-17
2003-07-22
Martin, David (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S794000, C174S250000
Reexamination Certificate
active
06597583
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layer circuit board and, more particularly, to a multi-layer circuit board having a capacitor incorporated therein. The present invention also relates to a process for manufacturing such a multi-layer circuit board.
2. Description of the Related Art
In a multi-layer circuit board on which a semiconductor element is mounted, a capacitor is incorporated therein so as to absorb noise. In a multi-layer circuit board known in the prior art, in order to absorb such noise, a chip capacitor is attached to the outside of the multi-layer circuit board.
However, in a multi-layer circuit board having a chip capacitor attached to the outside thereof, the distance between the semiconductor element and the capacitor is relatively large and, therefore, the noise absorbing effect is not sufficient. Also, there is another problem in that the size of the device including the capacitor is increased.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a multi-layer circuit board having a capacitor incorporated therein and a process for manufacturing the same, wherein the circuit board has a sufficient noise absorbing effect and the size thereof can be reduced.
Another object of the present invention is to provide a multi-layer circuit board and a process for manufacturing the same, wherein the above-mentioned drawbacks in the prior art can be avoided.
According to the present invention, there is provided a multi-layer circuit board comprising: at least one insulating layer having upper and lower surfaces thereof; wiring patterns arranged on the upper and lower surfaces of the insulating layer; a ferroelectric layer having a dieletric constant larger than that of the insulating layer and having upper and lower surfaces, the ferroelectric layer being arranged in the insulating layer in such a manner that the upper and lower surfaces of the ferroelectric layer coincide with the upper and lower surfaces of the insulating layer, respectively; and a pair of electrode films formed on the upper and lower surfaces of the ferroelectric layer, respectively, to define a capacitor incorporated in the circuit board.
According to another aspect of the present invention, there is provided a multi-layer circuit board comprising: at least one insulating layer having upper and lower surfaces thereof; wiring patterns arranged on the upper and lower surfaces of the insulating layer; a ferroelectric layer having a dieletric constant larger than that of the insulating layer and having a thickness smaller than that of the insulating layer, the ferroelectric layer being arranged within the thickness of the insulating layer; a pair of electrode films formed on the upper and lower surfaces of the insulating layer at a position to sandwich the ferroelectric layer via the insulating layer to define a capacitor incorporated in the circuit board.
In the above-mentioned multi-layer circuit board, one of the pair of electrode films and the wiring pattern which exists on the same surface of the one electrode film are electrically connected to a ground layer.
Also, in the above-mentioned multi-layer circuit board, the ferroelectric layer is made of a material selected from strontium titanate, lead zirconium titanate, tantalate oxide, or aluminum oxide.
According to another aspect of the present invention, there is provided a process for manufacturing a multi-layer circuit board comprising wiring patterns arranged in multi-layer by means of insulating layers, the process comprising: forming a ferroelectric layer on an upper conductor layer formed on a base support, in which the ferroelectric layer has a dieletric constant larger than that of the insulating layers and the base support is made of a material which is removable by etching; partially removing the ferroelectric layer so as to form a desired ferroelectric layer pattern; covering the ferroelectric layer pattern and the exposed upper conductor layer with an insulating layer; grinding the insulating layer so that the ferroelectric layer pattern is exposed; forming a lower conductor layer on the ground insulating layer; etching and removing the base support; and etching the upper and lower conductor layers to form desired wiring patterns in such a manner that electrode films of the wiring patterns are also formed to sandwich the ferroelectric layer pattern from respective sides thereof.
According to another aspect of the present invention, there is provided a process for manufacturing a multi-layer circuit board comprising wiring patterns arranged in multi-layer by means of insulating layers, the process comprising: forming a ferroelectric layer on a base support, in which the ferroelectric layer has a dielectric constant larger than that of the insulating layers and the base support is made of a material which is removable by etching; forming an upper insulating layer on the ferroelectric layer; forming a third conductor layer on the upper insulating layer; etching and removing the base support; partially removing the ferroelectric layer so as to form a desired ferroelectric layer pattern; covering the ferroelectric layer pattern and the exposed upper conductive layer with an insulating layer; forming a fourth conductor layer on the lower insulating layer; and etching the third and fourth conductor layers to form desired wiring patterns in such a manner that electrode films of the wiring patterns are also formed on the upper and lower insulating layers to sandwich the ferroelectric layer pattern from respective sides thereof via the upper and lower insulating layers.
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patent: 5638252 (1997-06-01), Drab et al.
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patent: 5926377 (1999-07-01), Nakao et al.
patent: 6215372 (2001-04-01), Novak
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patent: 10-93246 (2000-10-01), None
Lindinger Michael L.
Martin David
Paul & Paul
Shinko Electric Industries Co. Ltd.
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