Multilayer circuit board

Details Multilayer circuit board Multilayer circuit board

2000-12-20

2003-06-10

Martin, David (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S750000, C174S250000

Reexamination Certificate

active

06577508

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to multilayer circuit boards and, more particularly, to an improved multilayer circuit board for improving power and ground filtering performance by eliminating the need for electrically conductive vias.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, there is shown a conventional power filtering design wherein a multilayer circuit board has a power plane
12
and a ground plane
14
for providing power and ground to an integrated circuit component
16
mounted on the multilayer circuit board
10
. That is, the integrated circuit component
16
has a plurality of leads
18
, including a power lead
18
a
, a ground lead
18
b
, and a plurality of signals leads
18
c
. The integrated circuit component
16
is mounted on the multilayer circuit board
10
such that the power lead
18
a
is electrically connected to the power plane
12
, the ground lead
18
b
is electrically connected to the ground plane
14
, and the signal leads
18
c
are electrically connected to signal conductors (not shown) formed on other layers of the multilayer circuit board
10
. Thus, the power plane
12
provides power to the integrated circuit component
16
, while the ground plane
14
provides a ground for the integrated circuit component
16
.
When the integrated circuit component
16
is operating at high frequencies, high frequency noise often results on the power and ground planes
12
and
14
due to high speed internal switching within the integrated circuit component
16
, resulting unsteady current requirements. To alleviate this high frequency noise problem, bypass capacitors are often electrically connected between power planes and ground planes on multilayer circuit boards. For example, in
FIG. 1
, a bypass capacitor
20
is shown electrically connected between an electrically conductive via
22
that is electrically connected to the power plane
12
and an electrically conductive via
24
that is electrically connected to the ground plane
14
.
The purpose of the bypass capacitor
20
is to short together, at high frequencies, the power plane
12
and the ground plane
14
, thereby filtering out any high frequency noise. However, because of parasitic inductance, capacitance, and resistance associated with the vias
22
and
24
, the shorting capability, and thus the filtering capability, of the bypass capacitor
20
at high frequencies is diminished. Also, via inductance is more prevalent at high frequencies because the primary effect of series via inductance is that it degrades the effectiveness of power supply bypass capacitors, which defeats the whole power filtering strategy described above.
Attempts to solve the above-mentioned filtering problems have been pursued. For example, microvias have been used to shorten the length of vias, but they cannot eliminate vias completely. Also, via diameters have been reduced, thereby reducing the overall surface area over which parasitic inductance, capacitance, and resistance occur. However, changing the via diameter does little to influence via inductance. Thus, there remains a need for changing or eliminating the length of vias so as to improve power filtering performance.
In view of the foregoing, it would be desirable to provide a technique for improving power and ground filtering performance by changing or eliminating the length of electrically conductive vias which overcomes the above-described inadequacies and shortcomings.
SUMMARY OF THE INVENTION
According to the present invention, a technique for eliminating electrically conductive vias is provided. In one embodiment, the technique is realized as an improved multilayer circuit board for eliminating electrically conductive vias. The multilayer circuit board has a top layer and a buried layer separated by at least one dielectric layer, wherein the buried layer includes an electrically conductive power plane portion and an electrically conductive ground plane portion. The improvement comprises a cavity in the multilayer circuit board extending through the top layer and the at least one dielectric layer so as to expose at least a portion of the power plane portion and the ground plane portion of the buried layer within the cavity. The cavity is sized to accommodate an electronic component therein such that the electronic component makes electrical contact with the exposed portion of the power plane portion and the ground plane portion of the buried layer, thereby eliminating the need for electrically conductive vias electrically connected to the power plane portion and the ground plane portion of the buried layer.
In accordance with other aspects of the present invention, the buried layer beneficially includes a dielectric portion for separating the power plane portion and the ground plane portion.
In accordance with further aspects of the present invention, at least the lateral dimensions of the cavity are beneficially sized to directly coincide with at least the lateral dimensions of the electronic component. This is beneficially done whether the electronic component is an integrated circuit component or a discrete component, such as, for example, a capacitor for filtering noise from the power plane portion and the ground plane portion of the buried layer.
In accordance with still further aspects of the present invention, an electrically conductive shield is beneficially disposed on the top layer over the cavity for shielding electromagnetic interference to and from the electronic component.
In accordance with still further aspects of the present invention, wherein the electronic component is a first electronic component, a second electronic component is beneficially mounted on the top layer, wherein the second electronic component includes at least one electrically conductive lead extending into the cavity for electrical connection with the power plane portion or the ground plane portion of the buried layer. Furthermore, wherein the cavity is a first cavity, wherein the at least one dielectric layer is at least one first dielectric layer, wherein an additional layer is disposed above and separated from the top layer by at least one second dielectric layer, the improvement further comprises a second cavity in the multilayer circuit board extending through the additional layer and the at least one second dielectric layer so as to expose at least a portion of the top layer. In this case, the second cavity is sized to accommodate the second electronic component therein. Typically, the second cavity is sized so as to be larger in lateral dimension than the first cavity. In any event, an electrically conductive shield may be beneficially disposed on the additional layer over the second cavity for shielding electromagnetic interference to and from the first and second electronic components.
In an first alternative embodiment, the technique is realized as a method for eliminating electrically conductive vias in a multilayer circuit board. The multilayer circuit board has a top layer and a buried layer separated by at least one dielectric layer, wherein the buried layer includes an electrically conductive power plane portion and an electrically conductive ground plane portion. The method comprises forming a cavity in the multilayer circuit board extending through the top layer and the at least one dielectric layer so as to expose at least a portion of the power plane portion and the ground plane portion of the buried layer within the cavity. The cavity is sized to accommodate an electronic component therein such that the electronic component makes electrical contact with the exposed portion of the power plane portion and the ground plane portion of the buried layer, thereby eliminating the need for electrically conductive vias electrically connected to the power plane portion and the ground plane portion of the buried layer.
In accordance with other aspects of the present invention, the cavity may formed by etching the cavity in the multilayer circuit board. For example, the cavity may be etched by photolithographically etching

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