Multilayer analog interconnecting line layout for a...

Details Multilayer analog interconnecting line layout for a... Multilayer analog interconnecting line layout for a...

2006-09-19

2006-09-19

Ngô, Ngân V. (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Planar capacitor

C438S381000

Reexamination Certificate

active

07109088

ABSTRACT:
A mixed-signal integrated circuit includes a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor. The electrical path from one electrode of the capacitor passes through a first interconnecting line, then through multiple via holes to a second interconnecting line. During the fabrication process, the capacitor is first charged during a plasma deposition process used to deposit an interlayer dielectric film between the first and second interconnecting lines, then abruptly discharged during a plasma etching process that forms the via holes. The discharge does not damage the floors of the via holes, however, because each of the multiple via holes carries only part of the discharge current.

REFERENCES:
patent: 5598029 (1997-01-01), Suzuki
patent: 5917230 (1999-06-01), Aldrich
patent: 5946567 (1999-08-01), Weng et al.
patent: 6140693 (2000-10-01), Weng et al.
patent: 6387770 (2002-05-01), Roy
patent: 6709918 (2004-03-01), Ng et al.
patent: 2001/0023976 (2001-09-01), Kawata et al.
patent: 2002/0192919 (2002-12-01), Bothra

Affiliated with

Also associated with

Rating

Multilayer analog interconnecting line layout for a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilayer analog interconnecting line layout for a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayer analog interconnecting line layout for a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3553679